Design of Embedded Systems: Formal Models Validation, and Synthesis (0)

by S A Edwards, L Lavagno, E A Lee, A SangiovanniVincentelli
Venue:Proceedings of the IEEE 85(3) (March 1997), 366–390. Proof 26/05/2006; 11:19 File: jec65.tex; BOKCTP/ljl p