We propose a novel two-level Boolean minimizer coming in succession to our previously developed minimizer BOOM, so we have named it BOOM-II. It is a combination of two minimizers, namely BOOM and FC-Min. Each of these two methods has its own area where it is most efficiently applicable. We have combined these two methods together to be able to solve all kinds of problems efficiently, independently on their size or nature. The tool is very scalable in terms of the required runtime and/or the quality of the solution. It is applicable to functions with an extremely large number of both input and output variables.

We present a method allowing us to determine the grouping of the outputs of the multi-output Boolean logic function for a single-level partitioning and minimization. Some kind of decomposition is often needed during the synthesis of logic circuits and the subsequent mapping onto technology. Sometimes a circuit has to be divided into several stand-alone parts, among its outputs, or possibly its inputs. It could be a case of a design targeted into PLAs, GALs, or any other monolithic components having a limited number of inputs and/or outputs. We propose a methodology to determine the way how the original circuit has to be partitioned into several parts of an arbitrary size, in order to reduce the complexity of the individual parts. The method is based on our FC-Min minimizer, even when no Boolean minimization has to be involved here. The efficiency of the method is demonstrated on the standard MCNC benchmarks.

This paper describes principles of a novel two-level multi-output Boolean minimizer FC-Min, namely its Find Coverage phase. The problem of Boolean minimization is approached in a reverse way than common minimizers do. First, the cover of the on-set is found, and after that the appropriate implicants are being constructed to satisfy this cover. Thus, only the necessary group implicants are being generated, which makes FC-Min an extremely fast and efficient minimizer for functions with many output variables. An essential phase of the algorithm is the Find Coverage procedure. This phase determines the number of terms in the final solution, which has to be reduced to minimum. It solves an NP-hard problem, thus some heuristic has to be applied. We propose our heuristic method to solve this problem and study the influence of parameters on the final solution quality and runtime.

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We propose a modification of our Boolean minimizer BOOM-II enabling a single-level partitioning. The disadvantage of all the present logic synthesis systems is that the minimization and decomposition phases are strictly separated; the minimization process is independent on the subsequent decomposition. We propose a method where the two-level minimization is driven by some decomposition or other constraints. Here a two-level nature of a solution is retained, however, the circuit is divided into several stand-alone blocks, each block having several outputs. Our aim is to minimize the number of inputs for each block, as well as the blocks' logic. Copyright 2004 DESDes'04 Keywords: Boolean functions, minimization, decomposition, logic design 1.

A novel two-level Boolean minimization method is presented here.