Abstract. This paper shows how a previously specified theory for Abstract Reduction Systems (ARSs) in which noetherianity was defined by the notion of wellfoundness over binary relations is used in order to prove results such as the wellknown Newman’s Lemma and the Yokouchi’s Lemma. The former one known as the diamond lemma and the later which states a property of commutation between ARSs. Thears theory was specified in the Prototype Verification System (PVS) for which to the best of our knowledge there are no available theory for dealing with rewriting techniques in general. In addition to proof techniques available in PVS the verification of these lemmas implies an elaborated use of natural as well as noetherian induction. 1.

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Abstract. Recent works point out the application of rewriting-logic environments for the specification of hardware. When these specification are proved to be correct one can additionally apply them for the simulation, testing and even analysis of the conceived specified hardware. But theorem proving mechanisms are not included as basic/natural components of rewriting-logic environments (such as ELAN, CafeObj and Maude). Even worst, they are not able to handle proofs guided by basic methods of rewriting theory. Consequently, the correctness of these specifications have been done by hand. In this work we present a new practical methodology, which is based on a semantically intelligent translation of rewriting-logic specifications in ELAN to theories in the specification language PVS(a well-known proof assistant). This translation includes generation of lemmas to be checked for guaranteeing the joinability of critical pairs of the rewriting rules of the original specification. Resumo. Trabalhos recentes mostram como usar ambientes de reescrita lógica na especificação de hardware. As especificações, uma vez demonstradas corretas, podem ser simuladas, testadas e até analisadas no ambiente de reescrita. Entretanto sistemas de reescrita lógica (como ELAN, CafeObj e Maude) não incluem mecanismos naturais/básicos de prova de teoremas. Pior ainda, eles são incapazes de tratar provas orientadas pelos métodos básicos da teoria de reescrita. Por isto as provas de correção devem ser feitas de forma manual. Neste trabalho propomos uma metodologia prática, baseada da tradução semanticamente inteligente de especificações em reescrita lógica em ELAN para teorias na linguagem de especificação do PVS(um assistente de prova bem conhecido). Esta tradução inclui a geração de lemas a serem provados que garantem a juntabilidade dos pares críticos da especificação original em reescrita. 1.

A novel toolflow based in rewriting-logic is used to automatically generate polynomial approximations for arbitrary continous functions. The simple but powerful semantics of rewriting logic provide a natural mechanism for manipulating algebraic expressions, allowing the development to be done on a higher abstraction level while avoiding the unnecessary semantics required in hardware description and programming languages. The resulting polynomial approximations are rewritten to generate alternative implementation approaches which are automatically converted into different functionally equivalent hardware implementations. The rewriting-logic toolflow can generate implementations for both fine- and coarse-grained architectures. This paper presents the implementation results for the Pact XPP coarsegrained reconfigurable architecture.

This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations and the quick generation of functionally equivalent alternative implementations. The simple but powerful semantics of rewriting logic provide a natural mechanism for manipulating algebraic expressions, using a high-level of abstraction which is afterwards automatically converted into lower levels of abstraction. The design flow

Abstract — The exponential increase of CMOS circuit complexity along the last decades has lead to two growing problems. The increasing Non-recurring Engineering (NRE) costs of ASICs or System-on-Chips are becoming only affordable to the highest volume applications. Additionally the design methodologies have not kept pace with the rising complexity leading to a rising design productivity gap. Research into reconfigurable architectures and NoC (Network-on-Chip) communication systems have shown paths for mitigating these problems for lower volume applications. In this paper, we present the European Integrated Project MORPHEUS (IST 027342). It advocates an innovative approach of heterogeneous, dynamically reconfigurable SoCs consisting of accelerators of various reconfiguration granularity connected by a NoC and supported by an integrated toolset for spatial and sequential design. The power of this approach is demonstrated with four applications from the industrial environment.