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Abstract — Dessign techniques for low Powwer dissipation in moodern microprrocessors, espec cially in the design of diggital porrtable, notebook, and hand dheld computers are becomming inccreasingly impportant. As technology moves into deep subbmicron featuree sizes, the stati ic or leakage poower is expected to inccrease because of the exponen ntial increase in leakage curreents witth technology scaling. Wi ithin die-process variation is inccreasing in nannometer technologies, it is obsserve that leakkage powwer will become comparabl le to dynamic or total powwer disssipation in the next generat tion processorss in the next few yeaars. Therefore, it is important for system designeers to get an eaarly esttimate of leakkage power to meet the challenging and meethodologies for power dissipat tion reduction. This paper preesents a hardwa are design and implementationn of the complemenntary pass transistor control unit for microprocessors subthreshold le eakage currentt/power reducttion bassed on dual suupply voltage V ddL-VddH scalinng, and it can be connsidered as an effective mechanism for redducing processsors powwer and energy while preserv ving performannce by scaling the suppply voltage at runtime depend ding on the worrkload variationn. H-Leakage simmulation program is used to verrify the theoretiical ideea and confirm the hardware operations. Index Terms — — Complementa ary pass transisstor, Subthreshhold leaakage current, Dual supply voltage scaling. out the sources of powwer dissipationn, and the elemments of each source with its influennces. Theree are three soources of powwer dissipation in CMOS circuits. The total powwer dissipation of a CMOS circuit can be expressed as [2], P = total