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The System-On-Chip (SoC) design faces a gap between the production capabilities and time to market pressures. The design space, to be explored during the SoC design, grows with the improvements in the production capabilities and it takes an increasing amount of time to design a system that utilizes those capabilities. On the other hand shorter product life cycles are forcing an aggressive reduction of the time-to-market. Addressing this gap has been the aim of recent research work. As one approach abstract models have been introduced and a design flow was devised that guides the designer in the process from a most abstract model down to a synthesizable model. Throughout the design process computation and communication concerns are handled individually. The communication is mostly abstracted away from the designer, which allows the design focus to rest on the application specific computation. This separation requires the provider of an SoC design tool to supply fast and accurate communication models. Fast simulation capabilities are required for coping with the immense design space that is to be explored; these are especially needed during early stages of the design. This need has

Hardware/software partitioning is a crucial problem in embedded system design. In this paper, we provide an alternative approach to solve this problem using Particle Swarm Optimization (PSO) algorithm. Performance analysis of the proposed scheme with Integer Linear Programming, Genetic Algorithm and Ant Colony Optimization technique has been compared using standard benchmark datasets, and the computer simulations reveal that the proposed approach outperforms all the meta-heuristic based existing techniques with respect to cumulative runtimes for several runs of the same program. The Integer Linear Programming has been found to yield the optimal solutions, and the proposed swarm scheme yields suboptimal solution, sufficiently close to the reported results obtained for integer programming.

in quality

HW/SW partitioning of modern heterogeneous systems, which combine signal processing as well as multimedia applications, is usually performed on a task or process graph representation. As this optimisation problem is known to be NP-hard, existing partitioning techniques rely on heuristic methods to traverse the vast search space. The Global Criticality/Local Phase (GCLP) algorithm, initially introduced by Kalavade and Lee as an integral part of the Ptolemy work suite, has been frequently referred to as fast and powerful technique to generate high quality solutions for a combined partitioning/scheduling problem. In this work the internal mechanisms of the GCLP algorithm have been thoroughly analysed and several modifications are proposed that lead either to a significant increase of the quality of the obtained solutions without affecting the computation time of the algorithm or to a substantially lower computation time while increasing the output of valid partitioning solutions.

Abstract. This paper is devoted to the presentation of the key concepts on which a mathematical theory of complex (industrial) systems can be based. We especially show how this formal framework can capture the realness of modern information technologies. We also present some new modelling problems that are naturally emerging in the specific context of complex software systems.

We propose techniques for identifying and exploiting spatial and temporal reuse for indirectly indexed arrays. Indirectly indexed arrays are those arrays which are, typically, accessed inside multi-level loop nest and whose index expression includes not only loop iterators and constants but arrays as well. Existing techniques for improving locality are quite sophisticated in the case of directly indexed arrays. But, unfortunately, they are inadequate for handling indirectly indexed arrays. In this paper, we, therefore, extend the existing framework and techniques of directly indexed to indirectly indexed arrays. Concept of reuse subspace, dependence vector, self and group reuse are extended and applied in this new context. Also, lately scratch-pad memory has become an attractive alternative to data-cache, specially in the embedded multimedia community. This is because embedded systems are very sensitive to area and energy and the scratch-pad is smaller in area and consumes lesser energy on a per access basis compared to the cache of the same capacity. Several techniques have been proposed in the past for efficient exploitation of scratch-pad for directly indexed arrays. We extend these techniques by presenting a method for scratch-pad mapping of indirectly indexed arrays. This enables the scratch-pad to be used in a larger context than was possible before.

Abstract—In embedded consumer electronics devices, cost pressure is one of the driving design objectives. Devices that handle multimedia information, like DVD players or digital video cameras require high computing performance and realtime capabilities while adhering to the cost restrictions. The cost pressure often results in system designs that barely exceed the minimum requirements for such a system. Thus, hardware-based fault tolerance methods frequently are ignored due to their cost overhead. However, the amount of transient faults showing up in semiconductor-based systems is expected to increase sharply in the near future. Thus, lowoverhead methods to correct related errors in such systems are required. Considering restrictions in processing speed, the real-time properties of a system with added error handling are of special interest. In this paper, we present our approach to flexible error handling and discuss the challenges as well as the inherent timing dependencies to deploy it in a typical soft realtime multimedia system, a H.264 video decoder. I.

The research field of partitioning for electronic systems started to attract significant attention of scientists about fifteen years ago. Gaining ever more importance due to the rampant growth and shortening design cycles in wireless embedded systems, a multitude of formulations for this problem has emerged. Accordingly, a similar multitude can be found in the number of strategies that address system partitioning. A large proportion of the applied strategies utilise the concept of genetic algorithms, or, when based on different strategies, usually compare themselves to standard implementations of genetic algorithms. In this work, the internal mechanisms of this optimisation technique are thoroughly investigated and severe shortcomings of standard implementations are identified. Beneficial observations are made with respect to chromosome coding and mutation dedicated to typical problem graphs revealing a significant impact on the obtained solution quality. New problem oriented codings and operators are introduced and their performance is demonstrated on a task graph set of relevant process graphs. Finally, the modified genetic algorithm competes against Wiangtong’s tabu search, Axelsson’s simulated annealing, and Kalavade’s GCLP algorithm.

Smart devices are omnipresent today and the design of these embedded systems requires a multidisciplinary approach. It is important that students in electrical engineering and computer science learn these different aspects of embedded systems design. Our course on Complex Systems Design Methodology presents an overview of embedded systems design with a strong focus on the main concepts, preparing the students for more detailed follow-up courses on specific topics. Imparting the theoretical concepts to the students is not sufficient, however. Hands-on sessions are indispensable for the students to acquire the necessary skills. In this article we present our approach for these hands-on sessions, which is to pose relatively small problems in separate sessions, each focusing on a single design aspect. Five years after the introduction of this new course at Ghent University, we can conclude that students not only like this course, but that their design skills have also improved by our new, aspectfocused, approach.