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63
DPLL(T): Fast Decision Procedures
, 2004
"... The logic of equality with uninterpreted functions (EUF) and its extensions have been widely applied to processor verification, by means of a large variety of progressively more sophisticated (lazy or eager) translations into propositional SAT. Here we propose a new approach, namely a general DP ..."
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Cited by 116 (14 self)
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The logic of equality with uninterpreted functions (EUF) and its extensions have been widely applied to processor verification, by means of a large variety of progressively more sophisticated (lazy or eager) translations into propositional SAT. Here we propose a new approach, namely a general DPLL(X) engine, whose parameter X can be instantiated with a specialized solver Solver T for a given theory T , thus producing a system DPLL(T ). We describe this DPLL(T ) scheme, the interface between DPLL(X) and Solver T , the architecture of DPLL(X), and our solver for EUF, which includes incremental and backtrackable congruence closure algorithms for dealing with the builtin equality and the integer successor and predecessor symbols. Experiments with a first implementation indicate that our technique already outperforms the previous methods on most benchmarks, and scales up very well.
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors
 Journal of Symbolic Computation
, 2001
"... We compare SATcheckers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SATchecker that significantly outperforms the rest. We evaluate ways to enhance its per ..."
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Cited by 86 (12 self)
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We compare SATcheckers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SATchecker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.
A comparative study of two Boolean formulations of FPGA Detailed routing constraints
 International Symposium on Physical Design (ISPD), Sonoma Wine County
, 2001
"... A Booleanbased router expresses the routing constraints as a Boolean function which is satisfiable if and only if the layout is routable. Compared to traditional routers, Booleanbased routers offer two unique features: (1) simultaneous embedding of all nets regardless of net ordering, and (2) abil ..."
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Cited by 63 (32 self)
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A Booleanbased router expresses the routing constraints as a Boolean function which is satisfiable if and only if the layout is routable. Compared to traditional routers, Booleanbased routers offer two unique features: (1) simultaneous embedding of all nets regardless of net ordering, and (2) ability to demonstrate routing infeasibility by proving the unsatisfiability of the generated routing constraint Boolean function. In this paper, we introduce a new Booleanbased FPGA detailed routing formulation that yields an easytoevaluate and more scalable routability Boolean function than the previous methods. The routability constraints are expressed in terms of a set of “route ” variables each of which designating a specific detailed route for a given net. Experimental results clearly show the superiority of this formulation over an earlier formulation that expressed the constraints in terms of “track ” variables. 1.
EFFICIENT ALGORITHMS FOR CLAUSELEARNING SAT SOLVERS
, 2004
"... Boolean satisfiability (SAT) is NPcomplete. No known algorithm for SAT is of polynomial time complexity. Yet, many of the SAT instances generated as a means of solving realworld electronic design automation problems are simple enough, structurally, that modern solvers can decide them efficiently. ..."
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Cited by 57 (0 self)
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Boolean satisfiability (SAT) is NPcomplete. No known algorithm for SAT is of polynomial time complexity. Yet, many of the SAT instances generated as a means of solving realworld electronic design automation problems are simple enough, structurally, that modern solvers can decide them efficiently. Consequently, SAT solvers are widely used in industry for logic verification. The most robust solver algorithms are poorly understood and only vaguely described in the literature of the field. We refine these algorithms, and present them clearly. We introduce several new techniques for Boolean constraint propagation that substantially improve solver efficiency. We explain why literal count decision strategies succeed, and on that basis, we introduce a new decision strategy that outperforms the state of the art. The culmination of this work is the most powerful SAT solver publically available.
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
, 1999
"... In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition can be exploited when deciding its validity. We distinguish a class of terms we call "pterms" for which equality comparisons can ..."
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Cited by 54 (9 self)
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In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition can be exploited when deciding its validity. We distinguish a class of terms we call "pterms" for which equality comparisons can appear only in monotonically positive formulas. By applying suitable abstractions to the hardware model, we can express the functionality of data values and instruction addresses flowing through an instruction pipeline with pterms. A decision procedure can exploit the restricted uses of pterms by considering only "maximally diverse" interpretations of the associated function symbols, where every function application yields a different value except when constrained by functional consistency. We present a procedure that translates the original formula into one in propositional logic by interpreting the formula over a domain of fixedlength bit vectors and using vectors of proposit...
Differential symbolic execution
 In SIGSOFT ’08/FSE16: Proceedings of the 16th ACM SIGSOFT International Symposium on Foundations of software engineering
, 2008
"... Successful software systems tend to be long lived and evolve over time as requirements change and faults are detected. The number of times a system is updated and redeployed may be in the hundreds, or even thousands. Revalidation of an updated system, before it is released, is a critical component ..."
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Cited by 48 (2 self)
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Successful software systems tend to be long lived and evolve over time as requirements change and faults are detected. The number of times a system is updated and redeployed may be in the hundreds, or even thousands. Revalidation of an updated system, before it is released, is a critical component of the software evolution process. This step ensures that the changes made to the software have their intended effects, and that no unintended behaviors were introduced. Given the size and complexity of modern software systems, revalidation is generally costly and time consuming. Characterizing the differences between software versions can help focus revalidation tasks, potentially reducing the cost and effort necessary to redeploy the software. Change characterizations are also useful for other software evolution tasks, e.g., assessing the impact of the changes on other parts of the system. Existing change characterization techniques infer differences in program behaviors based on changes to the source code. This approach is imprecise, and therefore, can lead to unnecessary effort and cause delays in deployment. In this dissertation, we present a novel extension and application of symbolic
A Hybrid SATBased Decision Procedure for Separation Logic with Uninterpreted Functions
 In Proc. DAC’03
, 2003
"... SATbased decision procedures for quantifierfree fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on encoding atomic subformulas with Boolean variables, or by encoding integer variables as bitvectors. Based on evaluating the ..."
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Cited by 46 (4 self)
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SATbased decision procedures for quantifierfree fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on encoding atomic subformulas with Boolean variables, or by encoding integer variables as bitvectors. Based on evaluating these two encoding methods on a diverse set of hardware and software benchmarks, we conclude that neither method is robust to variations in formula characteristics. We therefore propose a new hybrid technique that combines the two methods. We give experimental results showing that the hybrid method can significantly outperform either approach as well as other decision procedures.
Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction
, 2000
"... . We extend the Burch and Dill flushing technique [9] for formal verification of highlevel microprocessors, based on the logic of Equality with Uninterpreted Functions and Memories (EUFM), to be applicable in an automatic fashion to designs where the functional units and memories have multicycle ..."
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Cited by 43 (14 self)
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. We extend the Burch and Dill flushing technique [9] for formal verification of highlevel microprocessors, based on the logic of Equality with Uninterpreted Functions and Memories (EUFM), to be applicable in an automatic fashion to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by effectively exploiting the properties of Positive Equality [5][6]. We study the modeling of the above features in different versions of dualissue superscalar microprocessors. Keywords. Formal verification, microprocessor verification, uninterpreted functions, logic of equality. 1 Introduction In order for formal methods to scale for verification of modern microprocessors, they need to be applicable easily and with a high degree of automation to designs with multicycle functional units, multicycle memories, exceptions, and branch prediction. Burch and Dill's verification methodology has...
Modeling and Verification of OutofOrder Microprocessors in UCLID
, 2002
"... In this paper, we describe the modeling and verification of outoforder microprocessors with unbounded resources using an expressive, yet efficiently decidable, quantifierfree fragment of first order logic. This logic includes uninterpreted functions, equality, ordering, constrained lambda express ..."
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Cited by 42 (13 self)
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In this paper, we describe the modeling and verification of outoforder microprocessors with unbounded resources using an expressive, yet efficiently decidable, quantifierfree fragment of first order logic. This logic includes uninterpreted functions, equality, ordering, constrained lambda expressions, and counter arithmetic. UCLID is a tool for specifying and verifying systems expressed in this logic. The paper makes two main contributions. First, we show that the logic is expressive enough to model components found in most modern microprocessors, independent of their actual sizes. Second, we demonstrate UCLID's verification capabilities, ranging from full automation for bounded property checking to a high degree of automation in proving restricted classes of invariants. These techniques, coupled with a counterexample generation facility, are useful in establishing correctness of processor designs. We demonstrate UCLID's methods using a case study of a synthetic model of an outoforder processor where all the invariants were proved automatically.
The UCLID Decision Procedure
 In CAV’04
, 2004
"... UCLID is a tool for termlevel modeling and verification of infinitestate systems expressible in the logic of counter arithmetic with lambda expressions and uninterpreted functions (CLU). In this paper, we describe a key component of the tool, the decision procedure for CLU. ..."
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Cited by 39 (1 self)
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UCLID is a tool for termlevel modeling and verification of infinitestate systems expressible in the logic of counter arithmetic with lambda expressions and uninterpreted functions (CLU). In this paper, we describe a key component of the tool, the decision procedure for CLU.