Results 1  10
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19
Background calibration techniques for multistage pipelined ADCs with digital redundancy
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculati ..."
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Cited by 15 (6 self)
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Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A twochannel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analogtodigital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radixbased digital background calibration. I.
Radixbased digital calibration technique for multistage ADC
 IEEE Int. Symp. Circuits Syst
, 2002
"... This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from th ..."
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Cited by 9 (4 self)
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This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digitaltoanalog converter (MDAC) architecture using ¢¡¤£¦¥¨§�©
A 0.9 V 9 mW 1 MSPS digitally calibrated ADC with 75 dB
 SFDR,” IEEE VLSI Circuits Symp
, 2003
"... A lowvoltage twostage algorithmic ADC incorporating the OpampReset Switching Technique (ORST) is presented. The lowvoltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switchedopamp. The ADC employs a highly linear input sampling circuit at t ..."
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Cited by 7 (6 self)
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A lowvoltage twostage algorithmic ADC incorporating the OpampReset Switching Technique (ORST) is presented. The lowvoltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switchedopamp. The ADC employs a highly linear input sampling circuit at the frontend, and the digital output is calibrated using a radixbased scheme. The prototype was fabricated in a 0.18µm CMOS technology and the active die area is 1.2mm × 1.2mm. The calibrated ADC demonstrates 75dB SFDR at 0.9V and 80dB SFDR at 1.2V. The total power consumption of the ADC is 9mW at the clock frequency of 7MHz (1MSPS). Keywords: Lowvoltage, opampreset switching technique, pipeline ADC, input sampling circuit, radixbased digital calibration.
SplitADC' Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC
 IEEE J. SolidState Circuits
, 2005
"... is demonstrated in a 16bit, 1MS/s algorithmic analogtodigital converter (ADC). Continuous digital background calibration is enabled by introduction of a “split ADC ” architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same inpu ..."
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Cited by 7 (4 self)
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is demonstrated in a 16bit, 1MS/s algorithmic analogtodigital converter (ADC). Continuous digital background calibration is enabled by introduction of a “split ADC ” architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for the background calibration process. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation process which adjust calibration parameters in each ADC. For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information. The analog subsystem of the ADC is implemented in 0.25 m CMOS, consumes 105 mW, and has a die size of 1.2 mm 1.4 mm. Index Terms—Adaptive systems, analogtodigital conversion, calibration, digital background calibration, mixed analog–digital integrated circuits, selfcalibrating. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
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Cited by 7 (0 self)
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A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
Background interstage gain calibration technique for pipelined ADCs
 IEEE Trans. Circuits and Syst. I
, 2005
"... A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The p ..."
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Cited by 5 (2 self)
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A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described in [1]. Simulation results are presented for a 12 bit pipelined ADC architecture, similar to that in [1], using nonideal interstage residue amplifiers. With calibration, the simulations show a SNDR performance of 72dB and a SFDR performance of 112dB, with calibration tracking time constants of approximately 8 x 10 5 sample periods, which is over 10 times faster than that reported in [1] at a similar performance level.
Digital Background Calibration of an Algorithmic AnalogtoDigital Converter Using a Simplified Queue
 IEEE J. SolidState Circuits
, 2003
"... An analog queuebased architecture and an adaptive digitalcalibration algorithm calibrate an 8bit twostage pipelined algorithmic analogtodigital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sampleandhold amplifier. At a sampling rate of 20 Msamples/ ..."
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Cited by 5 (2 self)
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An analog queuebased architecture and an adaptive digitalcalibration algorithm calibrate an 8bit twostage pipelined algorithmic analogtodigital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sampleandhold amplifier. At a sampling rate of 20 Msamples/s, the peak signaltonoiseanddistortion ratio (SNDR) is 45 dB, and the spuriousfree dynamic range (SFDR) is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm 2. Index Terms – Adaptive systems, analogdigital conversion, calibration, CMOS analog integrated circuits. I.
A 12bit 80MSample/s pipelined ADC with bootstrapped digital calibration
 IEEE Journal of SolidState Circuits
, 2005
"... This paper presents a prototype analogtodigital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closedloop gain errors, closedloop gain variation, and slewrate limiting. The prototype consists of an input sampleandhold amplifier (SHA) that can serve as a cali ..."
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Cited by 5 (0 self)
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This paper presents a prototype analogtodigital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closedloop gain errors, closedloop gain variation, and slewrate limiting. The prototype consists of an input sampleandhold amplifier (SHA) that can serve as a calibration queue, a 12bit 80Msample/s pipelined ADC, a digitaltoanalog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is −0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is −0.24 LSB. Also, the maximum signaltonoiseanddistortion ratio (SNDR) and spuriousfree dynamic range (SFDR) are 71.0 dB and 79.6 dB with a 40MHz sinusoidal input, respectively. The prototype occupies 22.6 mm 2 in a 0.25 µm CMOS technology and dissipates 755 mW from a 2.5 V supply.
A 13.5b 1.2V micropower extended counting A/D converter
 IEEE J. SolidState Circuits
, 2001
"... Abstract—This work presents a study of the extended counting technique for a 1.2V micropower voiceband A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. ..."
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Cited by 4 (1 self)
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Abstract—This work presents a study of the extended counting technique for a 1.2V micropower voiceband A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a firstorder 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8 m CMOS. With a 1.2V power supply, it consumes 150 W of power at a 16kHz Nyquist sampling frequency. The measured peak ƒ @x C „rhA was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about I Q I mmP of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area. Index Terms—Analogtodigital, extended counting, low power, low voltage. I.
Sub1v design techniques for highlinearity multistage/pipelined analogtodigital converters
 IEEE Transactions on Circuits and SystemsI
, 2005
"... Abstract—The design of an ultralowvoltage multistage (twostage algorithmic) analogtodigital converter (ADC) employing the opampreset switching technique is described. A highly linear input sampling circuit accommodates truly lowvoltage sampling from external input signal source. A radixbased ..."
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Cited by 3 (2 self)
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Abstract—The design of an ultralowvoltage multistage (twostage algorithmic) analogtodigital converter (ADC) employing the opampreset switching technique is described. A highly linear input sampling circuit accommodates truly lowvoltage sampling from external input signal source. A radixbased digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radixbased scheme is based on a halfreference multiplying digitaltoanalog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18 m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signaltonoiseplusdistortion ratio from 40 to 55 dB and the spuriousfree dynamic range from 47 to 75 dB. Index Terms—Analogtodigital converter (ADC), digital calibration, input sampling circuit, opampreset switching, pseudodifferential, ultralow voltage. I.