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32
Background Digital Calibration Techniques for Pipelined ADC's
 IEEE Trans. Circuits Syst. II
, 1997
"... A skip and fill algorithm is developed to digitally selfcalibrate pipelined analogtodigital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitorratioed multiplying digitaltoanalog converters (MDAC's) commonly used in multistep or pipelined ADC ..."
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Cited by 22 (4 self)
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A skip and fill algorithm is developed to digitally selfcalibrate pipelined analogtodigital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitorratioed multiplying digitaltoanalog converters (MDAC's) commonly used in multistep or pipelined ADC's. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other selfcalibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of selfcalibrating multistep or pipelined ADC's. The proposed method improves the performance of the inherently fast ADC's by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a splitreference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16bit accuracy using a 44th order polynomial interpolation, behaving essentially as an FIR filter.
Background calibration techniques for multistage pipelined ADCs with digital redundancy
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculati ..."
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Cited by 15 (6 self)
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Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A twochannel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analogtodigital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radixbased digital background calibration. I.
A cascaded sigmadelta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. ..."
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Cited by 13 (0 self)
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Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16b implementation of the architecture, fabricated in a 0.6"m CMOS process, cascades a secondorder 5b sigma–delta modulator with a fourstage 12b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clockboosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25MHz signal bandwidth and a total harmonic distortion (THD) of 098 dB with a 100kHz input signal. Index Terms—Analogdigital conversion, bootstrapped switch, digital filters, dynamic element matching, pipeline processing, sigma–delta modulation, switched capacitor circuits. I.
A/D Conversion with Imperfect Quantizers
 IEEE Transactions on Information Theory, Volume 52, Issue
, 2006
"... We analyze mathematically the effect of quantization error in the circuit implementation of Analog to Digital (A/D) converters such as Pulse Code Modulation (PCM) and Sigma Delta Modulation (Σ∆). Σ ∆ modulation, which is based on oversampling the signal, has a self correction for quantization error ..."
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Cited by 11 (1 self)
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We analyze mathematically the effect of quantization error in the circuit implementation of Analog to Digital (A/D) converters such as Pulse Code Modulation (PCM) and Sigma Delta Modulation (Σ∆). Σ ∆ modulation, which is based on oversampling the signal, has a self correction for quantization error that PCM does not have, and that we believe to be a major reason why Σ ∆ modulation is preferred over PCM in A/D converters with imperfect quantizers. Motivated by this, we construct other encoders that use redundancy to obtain a similar self correction property, but that achieve higher order accuracy relative to bit rate than “classical ” Σ∆. More precisely, we introduce two different types of encoders that exhibit exponential bit rate accuracy (in contrast to the polynomial rate of classical Σ∆) and still retain the self correction feature.
Radixbased digital calibration technique for multistage ADC
 IEEE Int. Symp. Circuits Syst
, 2002
"... This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from th ..."
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Cited by 9 (4 self)
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This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digitaltoanalog converter (MDAC) architecture using ¢¡¤£¦¥¨§�©
A digitally enhanced 1.8V 15bit 40MSample/s CMOS pipelined ADC
 Univ of Calif Los Angeles. Downloaded on November 5, 2009 at 13:59 from IEEE Xplore. Restrictions apply. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL
, 2004
"... analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is ..."
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Cited by 8 (0 self)
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analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digitaltoanalog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signaltonoise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a lowlatency, segmented, dynamic elementmatching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the firststage residue amplifier to settle. The IC is realized in a 0.18 m mixedsignal CMOS process and has a die size of 4mm 5 mm. Index Terms—Analogtodigital conversion, calibration, mixed analog–digital integrated circuits (ICs).
A 0.9 V 9 mW 1 MSPS digitally calibrated ADC with 75 dB
 SFDR,” IEEE VLSI Circuits Symp
, 2003
"... A lowvoltage twostage algorithmic ADC incorporating the OpampReset Switching Technique (ORST) is presented. The lowvoltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switchedopamp. The ADC employs a highly linear input sampling circuit at t ..."
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Cited by 7 (6 self)
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A lowvoltage twostage algorithmic ADC incorporating the OpampReset Switching Technique (ORST) is presented. The lowvoltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switchedopamp. The ADC employs a highly linear input sampling circuit at the frontend, and the digital output is calibrated using a radixbased scheme. The prototype was fabricated in a 0.18µm CMOS technology and the active die area is 1.2mm × 1.2mm. The calibrated ADC demonstrates 75dB SFDR at 0.9V and 80dB SFDR at 1.2V. The total power consumption of the ADC is 9mW at the clock frequency of 7MHz (1MSPS). Keywords: Lowvoltage, opampreset switching technique, pipeline ADC, input sampling circuit, radixbased digital calibration.
A 1.8V 67mW 10bit 100MS/s pipelined ADC using timeshifted CDS technique
 IEEE Journal of SolidState Circuits
, 2004
"... Abstract—A timeshifted correlated double sampling (CDS) technique is proposed in the design of a 10bit 100MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple casco ..."
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Cited by 7 (2 self)
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Abstract—A timeshifted correlated double sampling (CDS) technique is proposed in the design of a 10bit 100MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both highspeed and lowpower operation is achieved without compromising the accuracy requirement. An efficient commonmode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18 m CMOS process, the prototype 10bit pipelined ADC occupies 2.5 mmP of active die area. With 1MHz input signal, it achieves 65dB SFDR and 54dB SNDR at 100 MS/s. For 99MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline. Index Terms—Analogtodigital converter (ADC), correlated double sampling (CDS), data converter, high speed, low power, low voltage, pipeline. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
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Cited by 7 (0 self)
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A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
Background interstage gain calibration technique for pipelined ADCs
 IEEE Trans. Circuits and Syst. I
, 2005
"... A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The p ..."
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Cited by 5 (2 self)
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A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described in [1]. Simulation results are presented for a 12 bit pipelined ADC architecture, similar to that in [1], using nonideal interstage residue amplifiers. With calibration, the simulations show a SNDR performance of 72dB and a SFDR performance of 112dB, with calibration tracking time constants of approximately 8 x 10 5 sample periods, which is over 10 times faster than that reported in [1] at a similar performance level.