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21
Background calibration techniques for multistage pipelined ADCs with digital redundancy
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculati ..."
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Cited by 15 (6 self)
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Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A twochannel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analogtodigital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radixbased digital background calibration. I.
Radixbased digital calibration technique for multistage ADC
 IEEE Int. Symp. Circuits Syst
, 2002
"... This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from th ..."
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Cited by 9 (4 self)
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This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digitaltoanalog converter (MDAC) architecture using ¢¡¤£¦¥¨§�©
A lowpower reconfigurable analogtodigital converter
 IEEE J. Solid State Circuits
, 2001
"... Abstract—A lowpower CMOS reconfigurable analogtodigital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta– ..."
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Cited by 7 (0 self)
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Abstract—A lowpower CMOS reconfigurable analogtodigital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta–sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phaselocked loop (PLL). This converter also incorporates several powerreducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta–sigma mode, and other design techniques. The opamp chopping technique achieves faster closedloop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0–10 MHz over a resolution range of 6–16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta–sigma mode, it achieves a maximum signaltonoise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of 0.55 LSBs and 0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with
A 1.8V 67mW 10bit 100MS/s pipelined ADC using timeshifted CDS technique
 IEEE Journal of SolidState Circuits
, 2004
"... Abstract—A timeshifted correlated double sampling (CDS) technique is proposed in the design of a 10bit 100MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple casco ..."
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Cited by 7 (2 self)
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Abstract—A timeshifted correlated double sampling (CDS) technique is proposed in the design of a 10bit 100MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both highspeed and lowpower operation is achieved without compromising the accuracy requirement. An efficient commonmode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18 m CMOS process, the prototype 10bit pipelined ADC occupies 2.5 mmP of active die area. With 1MHz input signal, it achieves 65dB SFDR and 54dB SNDR at 100 MS/s. For 99MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline. Index Terms—Analogtodigital converter (ADC), correlated double sampling (CDS), data converter, high speed, low power, low voltage, pipeline. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
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Cited by 7 (0 self)
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A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
SplitADC' Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC
 IEEE J. SolidState Circuits
, 2005
"... is demonstrated in a 16bit, 1MS/s algorithmic analogtodigital converter (ADC). Continuous digital background calibration is enabled by introduction of a “split ADC ” architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same inpu ..."
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Cited by 7 (4 self)
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is demonstrated in a 16bit, 1MS/s algorithmic analogtodigital converter (ADC). Continuous digital background calibration is enabled by introduction of a “split ADC ” architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for the background calibration process. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation process which adjust calibration parameters in each ADC. For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information. The analog subsystem of the ADC is implemented in 0.25 m CMOS, consumes 105 mW, and has a die size of 1.2 mm 1.4 mm. Index Terms—Adaptive systems, analogtodigital conversion, calibration, digital background calibration, mixed analog–digital integrated circuits, selfcalibrating. I.
A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR
 IEEE J. SolidState Circuits
, 2005
"... Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling b ..."
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Cited by 5 (3 self)
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Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling branch demonstrates high linearity and inherent lowvoltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a twochannel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,
Digital Background Calibration of an Algorithmic AnalogtoDigital Converter Using a Simplified Queue
 IEEE J. SolidState Circuits
, 2003
"... An analog queuebased architecture and an adaptive digitalcalibration algorithm calibrate an 8bit twostage pipelined algorithmic analogtodigital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sampleandhold amplifier. At a sampling rate of 20 Msamples/ ..."
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Cited by 5 (2 self)
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An analog queuebased architecture and an adaptive digitalcalibration algorithm calibrate an 8bit twostage pipelined algorithmic analogtodigital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sampleandhold amplifier. At a sampling rate of 20 Msamples/s, the peak signaltonoiseanddistortion ratio (SNDR) is 45 dB, and the spuriousfree dynamic range (SFDR) is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm 2. Index Terms – Adaptive systems, analogdigital conversion, calibration, CMOS analog integrated circuits. I.
Sub1v design techniques for highlinearity multistage/pipelined analogtodigital converters
 IEEE Transactions on Circuits and SystemsI
, 2005
"... Abstract—The design of an ultralowvoltage multistage (twostage algorithmic) analogtodigital converter (ADC) employing the opampreset switching technique is described. A highly linear input sampling circuit accommodates truly lowvoltage sampling from external input signal source. A radixbased ..."
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Cited by 3 (2 self)
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Abstract—The design of an ultralowvoltage multistage (twostage algorithmic) analogtodigital converter (ADC) employing the opampreset switching technique is described. A highly linear input sampling circuit accommodates truly lowvoltage sampling from external input signal source. A radixbased digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radixbased scheme is based on a halfreference multiplying digitaltoanalog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18 m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signaltonoiseplusdistortion ratio from 40 to 55 dB and the spuriousfree dynamic range from 47 to 75 dB. Index Terms—Analogtodigital converter (ADC), digital calibration, input sampling circuit, opampreset switching, pseudodifferential, ultralow voltage. I.
NETAN: Multinet threedimensional field solver extraction tool, Users reference manual, OEA
 IEEE Trans. Circuits Syst. II, Express Briefs
, 2001
"... Abstract — The “Split ADC ” architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of t ..."
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Cited by 2 (1 self)
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Abstract — The “Split ADC ” architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background calibration algorithm. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation algorithm, which adjusts digital calibration parameters in an adaptive process similar to a least mean square (LMS) algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16b, 1MS/s algorithmic ADC. Simulated results are presented confirming selfcalibration in approximately 10,000 conversions, which represents an improvement of four orders of magnitude over previous statisticallybased calibration algorithms. Index Terms — Analog–digital conversion, adaptive systems, calibration, selfcalibrating, digital background calibration, mixed analogdigital integrated circuits.