Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50 % of the dynamic power. Over 90 % of the interconnect power is consumed by only 10 % of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router’s algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14 % in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.

This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new approximate scheme to perform the delay calculations with stochastic delay values in linear time. The results are validated with Monte Carlo simulations. From a mathematical analysis some counter--intuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worst--case timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits for a given delay model. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0 -- 14%. Furthermore, due to the mathematical properties of the delay...

In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a robust linear program that can be solved efficiently. We demonstrate the efficiency and computational tractability of the proposed algorithm on the various ISCAS’85 benchmark circuits. Across the benchmarks, compared to the deterministic approach, the power savings range from 23 − 30 % for the same timing target and the yield level, the average power saving being 28%. The runtime is reasonable, ranging from a few seconds to around 10 mins, and grows linearly.

A three-step algorithm is presented for discrete gate sizing problem of delay#area optimization under double-sided timing constraints. The problem is #rst formulated as a linear program. The solution to the linear program is then mapped onto a permissible set. Using this permissible set, the gate sizes are adjusted to satisfy the delaylower and upper bounds simultaneously.

The problem of sizing gates for power-delay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimumpower circuit is not necessarily the minimum-sized circuit.

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.

Abstract{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized by an inertial delay and separate delays between its inputs and output. The technology constraint, related tofeasible ranges of lengths and widths of transistors, is speci ed bya parameter u b.Itistheupper bound on the di erence between the input to output delays corresponding to any pair of inputs of a gate. We formulate a linear program (LP) whose size is proportional to the circuit size. This LP determines the inertial delay as well as input to output delays for each gate of the circuit with the given u b, such that all glitches are eliminated and the overall delay of the circuit is minimized. Because of the additional exibility in specifying gate delays, the glitch suppression is guaranteed without any delay bu ers. Hence this design consumes less power than those designed by other methods. We designed the circuit c1355 with 46 % of the original power dissipation compared toareference design. A previously published method, that characterizes each gate with a single delay, produced a c1355 circuit consuming 58% of the original power. Both low-power circuits had the same overall delay. The previous design required 224 delay bu ers, whereas the new design needed none. 1.

The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circuit power are considered, and a new modeling technique is used to calculate the short-circuit power. The notion of transition density is used, with an enhancement that considers the effect of gate delays on the transition density. When the short-circuit power is neglected, the minimum power circuit is identical to the minimum area circuit. However, under our more realistic models, our experimental results on several circuits show that the minimum power circuit is not necessarily the same as the minimum area circuit.