Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnection networks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper, we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3X power savings (4.6X on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanisms, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain.

Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoCbased systems, including task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28 % on average compared with existing techniques.

Power consumption is a key issue in high-performance interconnection network design. Communication links, already a significant consumer of power now, will take up an ever larger portion of the power budget as demand for network bandwidth increases. In this paper, we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS algorithm that judiciously adjusts DVS policies based on past link utilization. Despite very conservative assumptions about DVS link characteristics, our approach realizes up to 4.3X power savings (3.2X average), with just an average 27.4% latency increase and 2.5% throughput reduction. To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

Abstract — We compare techniques that dynamically scale the voltage of individual network links to reduce power consumption with an approach in which all links in the network are set to the same voltage and adaptive routing is used to distribute load across the network. Our results show that adaptive routing with static network link voltages outperforms dimension-order routing with dynamic link voltages in all cases, because the adaptive routing scheme can respond more quickly to changes in network demand. Adaptive routing with static link voltages also outperforms adaptive routing with dynamic link voltages in many cases, although dynamic link voltage scaling gives better behavior as the demand on the network grows. I.

As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increasing, optical links are replacing electrical links in inter-chassis and inter-board environments. As a result, the power dissipation of optical links is becoming as critical as their speed. In this paper, we first explore options for building high speed opto-electronic links and discuss the power characteristics of different link components. Then, we propose circuit and network mechanisms that can realize power-aware optical links – links whose power consumption can be tuned dynamically in response to changes in network traffic. Finally, we incorporate power-control policies along with the power characterization of link circuitry into a detailed network simulator to evaluate the performance cost and power savings of building power-aware opto-electronic networked systems. Simulation results show that more than 75% savings in power consumption can be achieved with the proposed power-aware opto-electronic network. 1

Interconnection networks have been deployed as the communication fabric in a wide spectrum of parallel computer systems, ranging from chip multiprocessors (CMPs) and embedded multicore systems-on-a-chip (SoCs) to clusters and server blades. Recent technology trends have permitted a rapid growth of chip resources, faster clock rates, and wider communication bandwidths, however, these trends have also led to an increase in power consumption that is becoming a key limiting factor in the design of such scalable interconnected systems. Power-aware networks, therefore, need to become inherent components of single and multi-chip parallel systems. In the hardware arena, recent interconnection network power-management research work has employed limitedscope techniques that mostly focus on reducing the power consumed by the network communication links. As these limited-scope techniques are not tailored to the applications running on the network, power savings and the corresponding impact on network latency vary significantly from one application to the next as we demonstrate in this paper; in many cases, network performance can severely suffer. In the software arena, extensive research on compile-time optimizations has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy. In this paper, we take the first steps toward tailoring applications ’ communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing Extension of Conference Paper. Original work appeared in CASES’05 [Soteriou et al. 2005]. The extensions found in the journal paper submission are the following:

Abstract—A hybrid analog–digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 m CMOS process achieves BER 10 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than 5000 ppm and 2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking. Index Terms—Clock and data recovery, phase-locked loop (PLL), spread-spectrum clocking, digital phase interpolation, delta-sigma. Fig. 1. Serial signaling system with embedded clock. I.

Techniques like dynamic voltage scaling (DVS) and modulation scaling provide the ability to perform an energy-delay tradeoff in the computation and communications subsystems. Slowdown based on performance requirements has shown to be energy efficient while meeting timing requirements. We address the problem of computing slowdown factors for a non-preemptive task system based on the Earliest Deadline First scheduling policy. We present a stack based slowdown algorithm based on the optimal feasibility test for non-preemptive systems. We also propose a dynamic slack reclamation policy to further enhance the energy savings. The algorithms are practically fast, and have the same time complexity as the feasibility test for non-preemptive systems. The simulation results for our test examples show on an average 15% energy gains using static slowdown factors and 20% gains with dynamic slowdown over the known slowdown techniques.

As the functionality of digital chips continues to increase dramatically, chip-to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be-come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are important as bit periods continue to shrink. Furthermore, in order for these circuits to have a true impact on the performance of the system, they must use unique architectures to achieve timing accuracy rather than simply trading power consumption for performance. This thesis discusses issues related to the timing circuits on both the transmit and receive side of the link. On the transmit side, a phase-locked loop (PLL) is used to generate the clock that tells the driver when to start and stop driving the current bit onto the channel. On the receive side, a clock and data recovery (CDR) circuit is responsible for properly centering the sampling clock in the middle of the bit period. Design techniques to achieve good timing performance in both the PLL and CDR are proposed. Specifically, the PLL incorporates a supply regulated tuning scheme to combat the high levels of supply noise present in large digital chips and a resistor-based charge pump to reduce the charge pump flicker noise contribution. The CDR uses oversampling to decouple the tradeoff between two important performance metrics: jitter generation and jitter tolerance. To validate the proposed ideas, both a PLL test chip and a CDR test chip are presented. The PLL operates from 0.5GHz to 2.5GHz and achieves 2.36ps rms jitter using a ring voltage-controlled oscillator. The power consumption scales favorably with frequency, using much less power at lower frequencies where less power is needed. The CDR operates up to 3.6Gbps with a BER of less than 10-12. The measured jitter tolerance corner frequency was improved by a factor of 30 from 1MHz to 30MHz without increasing the recovered clock jitter.