Results 1  10
of
12
A digitally enhanced 1.8V 15bit 40MSample/s CMOS pipelined ADC
 Univ of Calif Los Angeles. Downloaded on November 5, 2009 at 13:59 from IEEE Xplore. Restrictions apply. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL
, 2004
"... analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is ..."
Abstract

Cited by 11 (0 self)
 Add to MetaCart
(Show Context)
analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digitaltoanalog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signaltonoise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a lowlatency, segmented, dynamic elementmatching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the firststage residue amplifier to settle. The IC is realized in a 0.18 m mixedsignal CMOS process and has a die size of 4mm 5 mm. Index Terms—Analogtodigital conversion, calibration, mixed analog–digital integrated circuits (ICs).
Simplified logic for firstorder and secondorder mismatchshaping digitaltoanalog converters
 IEEE Trans. Circuits Syst. II, Expr. Briefs
, 2001
"... ..."
DeltaSigma Data Conversion in Wireless Transceivers
, 2002
"... Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wirel ..."
Abstract

Cited by 5 (2 self)
 Add to MetaCart
Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.
Segmented Dynamic Element Matching for HighResolution DigitaltoAnalog Conversion
"... Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require ..."
Abstract

Cited by 4 (4 self)
 Add to MetaCart
Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require lowresolution but highlinearity DACs. More recently, segmented DEM architectures have made highresolution Nyquistrate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. Index Terms—Digitaltoanalog conversion, dynamic element matching (DEM), segmentation. I.
A tight signalband power bound on mismatch noise in a mismatch shaping digitaltoanalog converter
 IEEE Trans. Inf. Theory
, 2004
"... Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
(Show Context)
Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signaltonoise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatchshaping DACs exploit builtin redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatchshaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatchshaping DAC: the dithered firstorder lowpass treestructured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dcfree sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signalband DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analogtodigital, data converters, dcfree sequences, delta–sigma (16), digitaltoanalog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.
TreeStructured DEM DACs with Arbitrary Numbers of Levels
"... Abstract—Unityweighted treestructured dynamic element matching (DEM) DACs are widely used in deltasigma (16) data converters to ensure that mismatches among nominally identical analog components give rise to shaped noise instead of nonlinear distortion. Treestructured DEM DACs offer an advantage ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
Abstract—Unityweighted treestructured dynamic element matching (DEM) DACs are widely used in deltasigma (16) data converters to ensure that mismatches among nominally identical analog components give rise to shaped noise instead of nonlinear distortion. Treestructured DEM DACs offer an advantage over other published DEM DACs in that the shaped noise from component mismatches can be made free of spurious tones. However, previously published unityweighted treestructured DEM DACs have the disadvantage that they require a poweroftwo number of nominally identical 1bit DACs. When applied to a 16 data converter with a nonpoweroftwo number of quantization steps, this requires the DEM DAC to have a larger input range than needed by the 16 data converter which wastes power and circuit area. This paper presents a generalized treestructured DEM encoder applicable to DEM DACs with any number of 1bit DACs, thereby avoiding this limitation. Index Terms—Digitaltoanalog conversion, dynamic element matching (DEM), encoder. I.
A 3 rd order 3bit SigmaDelta Modulator with Reduced Delay Time of Data Weighted Averaging
"... Abstract—This paper presents a method of reducing the feedback delay time of DWA(Data Weighted Averaging) used in sigmadelta modulators. The delay time reduction results from the elimination of the latch at the quantizer output and also from the falling edge operation. The designed sigmadelta modu ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract—This paper presents a method of reducing the feedback delay time of DWA(Data Weighted Averaging) used in sigmadelta modulators. The delay time reduction results from the elimination of the latch at the quantizer output and also from the falling edge operation. The designed sigmadelta modulator improves the timing margin about 16%. The subcircuits of sigmadelta modulator such as SC(Switched Capacitor) integrator, 9level quantizer, comparator, and DWA are designed with the nonideal characteristics taken into account. The sigmadelta modulator has a maximum SNR (Signal to Noise Ratio) of 84 dB or 13 bit resolution. Keywords—Sigmadelta modulator, multibit, DWA I.
A/D Converter With a Modified Noise Transfer Function
"... Abstract—This paper presents a highorder doublesampling singleloop 61 modulation analogtodigital (A/D) converter. The important problem of noise folding in doublesampling circuits is solved here at the architectural level by placing one of the zeros in the modulator’s noise transfer function a ..."
Abstract
 Add to MetaCart
Abstract—This paper presents a highorder doublesampling singleloop 61 modulation analogtodigital (A/D) converter. The important problem of noise folding in doublesampling circuits is solved here at the architectural level by placing one of the zeros in the modulator’s noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourthorder modulator. Through the use of an efficient switchedcapacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourthorder modulator. An experimental 1bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3V supply in a conservative 0.8 m standard CMOS process. Due to the doublesampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signaltonoise ratio and signaltonoiseplusdistortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total. Index Terms—analogtodigital conversion, double sampling, sigmadelta modulation. I.
A, Overview of Feedforward Design Techniques for HighGain Wideband Operational Transconductance Amplifiers An Overview of Feedforward Design Techniques for HighGain Wideband Operational Transconductance Amplifiers
"... ABSTRACT: In this paper, feedforward techniques are revised and used for the design of highfrequency Operational Transconductance Amplifiers (OTA). For the same power consumption and similar transistor dimensions the twopath and threepath foldedcascode OTAs present both smaller settling error a ..."
Abstract
 Add to MetaCart
ABSTRACT: In this paper, feedforward techniques are revised and used for the design of highfrequency Operational Transconductance Amplifiers (OTA). For the same power consumption and similar transistor dimensions the twopath and threepath foldedcascode OTAs present both smaller settling error and faster response as compared with the typical foldedcascode topology. Also, a NoCapacitor FeedForward (NCFF) compensation, which uses a highfrequency polezero doublet to obtain high gain, high GBW and a good phase margin, is discussed. The settlingtime of the NCFF topology can be faster than that of higher miller based OTAs, even if the last topology uses larger transconductance values. Experimental results for the multitrajectory OTAs fabricated in the AMI 0.5 µm CMOS process demonstrate the feasibility of the feedforward schemes.