A cellular hardware implementation of a spiking neural network with run-time reconfigurable connectivity is presented. It is implemented on a compact custom FPGA board which provides a powerful reconfigurable hardware platform for hardware and software design. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing the network with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the Khepera robot for a task of obstacle avoidance. Finally, future implementations on new multi-cellular hardware are discussed.

Abstract. The structure and operation of multi-cellular organisms relies, among other things, on the specialization of the cells ’ physical structure to a finite set of specific operations. If we wish to make the analogy between a biological cell and a digital processor, we should note that nature’s approach to parallel processing is subtly different from conventional von Neumann architectures or even from conventional parallel processing approaches, where specialization is obtained by adapting software to a fixed hardware structure. In this article we will present the outline of a novel processor architecture based on the Move or TTA (Transport-Triggered Architecture) approach. The features of such architectures allow them to implement systems that more closely resemble, within the limitations imposed by the capabilities of conventional silicon, the general modus operandi of multi-cellular organisms. 1

A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial run-time reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices.

A hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital

The choice of an appropriate hardware representation model is key to successful evolution of digital circuits. One of the most popular models is cartesian genetic programming, which encodes an array of logic gates into a chromosome. While several smaller circuits have been successfully evolved on this model, it lacks scalability. A recent approach towards scalable hardware evolution is based on the automated creation of modules from primitive gates. In this paper, we present two novel approaches for module creation, an age-based and a cone-based technique. Further, we detail a cone-based crossover operator for use with cartesian genetic programming. We evaluate the different techniques and compare them with related work. The results show that age-based module creation is highly effective, while cone-based approaches are only beneficial for regularly structured, multiple output functions such as multipliers.

Abstract — This paper presents a hardware implementation of evolvable block-based neural network (BBNN) amd a kind of EDAs called cellular compact genetic algorithm (CCGA) in FPGA. The CCGA and BBNN have cellular-like and array-like structures which are suitable for hardware implementation. The implemented hardware demonstrates the completely intrinsic online evolution in hardware without software running on microprocessors. This work contributes to the field of evolvable hardware by proposing CCGA and a layer-based architecture to an integration of BBNN and CCGA as a kind of evolvable hardware. In addition, the proposed CCGA efficiently solves the scalable issues by scaling up to the size of BBNN. The presented approach demonstrates a new kind of evolvable hardware. I.

This paper presents a cellular compact genetic algorithm (CCGA) for evolvable and adaptive hardware. The CCGA has cellular-like structure which is suitable for hardware implementation. The CCGA is developed from compact genetic algorithm (CGA) and parallel estimation of distribution algorithm (EDA). The concept and algorithm of the CCGA are presented. The standard test functions are selected to measure the effectiveness of the CCGA. The experimental results significantly shows that the CCGA outperforms the normal compact GA and deliver compatible results to the cooperative compact genetic algorithm while employs only one type of cell. The implemented hardware in FPGA demonstrates the feasibility to use this new kind of genetic algorithm to evolvable and adaptive hardware. 1.

Typical non-linear image processing applications include the correction of non-linear distortion introduced by components, communication channels and compensation for non-linearity in input output devices. Every digital signal or image processing operation can be viewed at its most basic level as the manipulation of a series of finite-length binary strings. Whether the operation is implemented on a processor through software or in dedicated hardware, the data and the algorithms are invariably mapped through electronic logic components, which are inherently binary in nature. In nonlinear image and signal processing, the design of operators is carried out by seeking the optimum mapping from one set of binary strings to another. This contrasts with the linear approach which formulates a solution by optimizing coefficients within a generalized multiply-accumulate context. Traditional adaptive filter works in a rectangular window whose size varies during filter operation depending on certain conditions. The optimal size of the window is crucial and influences the computation and memory requirements. However, this optimal size selection is highly application specific and its convergence from an initial value requires experimentation with various sizes of standard filters. Nonlinear image processing is presented in this paper as a generalization of the above operation by removing the linearity constraints. It seeks the optimum mapping implemented directly in logic. The linear solution should be viewed as a special case of the set of all logic based solutions rather than as an alternative. This generalization, the optimum nonlinear solution will be either better or equivalent to the linear solution, but it should not be worse. This inequality holds regardless of the problem or the criteria, provided that the training data is sufficient.