Results 1 
7 of
7
High speed array of oscillatorbased truly binary random number generators
 Proceedings of 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004
, 2004
"... A technique to produce many high speed uncorrelated truly binary random number generators (RNGs) utilizing least area and power is proposed. The technique relies on the phase noise and jitter of voltage controlled oscillators (VCOs) to generate RNGs using the oscillator sampling technique. To obtain ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
(Show Context)
A technique to produce many high speed uncorrelated truly binary random number generators (RNGs) utilizing least area and power is proposed. The technique relies on the phase noise and jitter of voltage controlled oscillators (VCOs) to generate RNGs using the oscillator sampling technique. To obtain true randomness, the frequency of oscillation of the VCOs is controlled by other RNGs in the array, increasing the jitter spread much more than conventional designs. Parallel high speed uncorrelated random sequences are tested at 1GHz in CMOS 0.18µm process. Fig.1 RNG technique using direct sampling 1.
A 285MHz Pipelined MAP Decoder in 0.18 m CMOS
"... Abstract—Presented in this paper is a pipelined 285MHz maximum a posteriori probability (MAP) decoder IC. The 8.7mm2 IC is implemented in a 1.8V 0.18 m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a blockinterleaved pipelined architecture, which enable ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract—Presented in this paper is a pipelined 285MHz maximum a posteriori probability (MAP) decoder IC. The 8.7mm2 IC is implemented in a 1.8V 0.18 m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a blockinterleaved pipelined architecture, which enables the pipelining of the addcompareselect kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energyefficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18 m designs with the smallest area; and 3) comparable throughput with an area reduction of 34 3 with reference to a lookahead based highspeed design (Radix4 design), and a parallel architecture. Index Terms—CMOS, iterative processing, maximum a posteriori probability (MAP) decoder, pipeline, turbo decoder, turbo equalizer. I.
VoltageControlled Ring Oscillator for Low Phase Noise Application
"... A design for a voltagecontrolled ring oscillator (VCO) is presented. The design allows an implementation of low frequency ring oscillator using relatively small devices and less stage. It is implemented using.18um technology provided by TSMC technology using 3.3V power supply. The VCO topology exhi ..."
Abstract
 Add to MetaCart
(Show Context)
A design for a voltagecontrolled ring oscillator (VCO) is presented. The design allows an implementation of low frequency ring oscillator using relatively small devices and less stage. It is implemented using.18um technology provided by TSMC technology using 3.3V power supply. The VCO topology exhibits a very wide tuning range from few Hz to 368.9 MHz. It also features the rapid voltage swing and the 48 % duty cycle with good transient characteristics which is difficult to get from the conventional oscillator. Its power dissipation at the maximum oscillation frequency is 35.05 mW. A frame work for modeling the phase noise in complementary metal–oxide–semiconductor (CMOS) ring oscillators. Phase noise for simulated circuit is88dbc when offset frequency is 10 5 HZ.
WITH A COMBINED CHOPPING AND AVERAGING TECHNIQUE FOR REDUCED DISTORTION IN 0.18µm CMOS
, 2005
"... Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6bit AnalogtoDigital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, faulttolerant scheme to achieve high SFDR in an averaging flash A/D converter using comparator chopping. Chopp ..."
Abstract
 Add to MetaCart
(Show Context)
Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6bit AnalogtoDigital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, faulttolerant scheme to achieve high SFDR in an averaging flash A/D converter using comparator chopping. Chopping of comparators in a flash A/D converter was never previously implemented due to lack of feasibility in implementing multiple, uncorrelated, high speed random number generators. This work proposes a novel array of uncorrelated truly binary random number generators working at 1GHz to chop all comparators. Chopping randomizes the residual offset left after averaging, further pushing the dynamic range of the converter. This enables higher accuracy and lower biterror rate for high speed diskdrive read channels. Power consumption and area are reduced because of the relaxed design requirements for the same linearity. The technique has been verified in Matlab simulations for a 6bit 1Gsamples/s flash ADC under case of process gradients with nonzero mean offsets as high as 60mV and potentially serious spot offset errors as high as 1V for a 2V peak to peak input
Rim Ayadi
"... Analog and mixed architectures design with high performance suffered from many difficulties due to low power supply, consumption, and the trend toward reducing the size of the circuit. Currently, these performances are considered one of the main constraints in analog design. Characterized and design ..."
Abstract
 Add to MetaCart
(Show Context)
Analog and mixed architectures design with high performance suffered from many difficulties due to low power supply, consumption, and the trend toward reducing the size of the circuit. Currently, these performances are considered one of the main constraints in analog design. Characterized and designed of mixed circuits such as Charge PumpPhase Locked Loops (CPPLLs) is a challenge in mixedsignal integrated circuits design. In this paper, an effective CMOS CPPLLs architecture for RF applications that operates at a low power supply 2V into a large range frequency is presented. The proposed CPPLLs architecture has two novel design blocks which are respectively Phase Frequency Detector (PFD) and Voltage Controlled Oscillator (VCO). The key advantage of the two novel designs is that uses a simple circuit, provide more stable operation compared with other structures recently used and reduce the chip area overhead. Also, the novel VCO design solved the problems caused by recent structures. The CPPLLs is designed and evaluated using electrical simulator tolls (ADS) with 0.35μm AMS CMOS technology. Simulations results show a good performance and the effectiveness of the proposed structure.
Analog Integr Circ Sig Process DOI 10.1007/s1047000891856
"... Abstract A 3phase current controlled sinusoidal oscillator, tunable over a wide range of frequencies is presented. The oscillator comprises a ring of 3 cascaded differential Gm C lowpass filter stages, implemented in a fully translinear, NPNonly circuit. Closedform analytical expressions are de ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract A 3phase current controlled sinusoidal oscillator, tunable over a wide range of frequencies is presented. The oscillator comprises a ring of 3 cascaded differential Gm C lowpass filter stages, implemented in a fully translinear, NPNonly circuit. Closedform analytical expressions are derived to quantify both frequency and amplitude tuning, as a function of two current biases. Experimental results from a 0.5 lm SiGe BiCMOS chip demonstrate 7 decades of tuning range, from 80 Hz to 800 MHz, as well as low harmonic distortion. Power consumption scales with oscillation frequency, measuring 2 lW/MHz The circuit serves a range of applications including agile communications, analog builtin selftest, stochastic adaptive control, spectroscopy, and bioinstrumentation.
unknown title
"... Abstract — A new design of a Voltage Controlled Ring Oscillator is proposed in this paper in order to improve the oscillation frequency characteristic. The structure and the operation of proposed Voltage Controlled Ring Oscillator have been described. The new VCO is implemented and simulated by usin ..."
Abstract
 Add to MetaCart
Abstract — A new design of a Voltage Controlled Ring Oscillator is proposed in this paper in order to improve the oscillation frequency characteristic. The structure and the operation of proposed Voltage Controlled Ring Oscillator have been described. The new VCO is implemented and simulated by using ADS platform with 0.35μm AMS CMOS technology; this circuit uses relatively small devices dimensions and low power supply 2V to operate in a large range frequency. In addition, the proposed structure enables the output signal of the VCO to oscillates between ‘‘0’ ’ and ‘‘1’ ’ for each input value of control voltage Vinvco, varied between 0V to 1,3V, which is difficult to get from the Conventional Voltage Controlled Oscillator. Input control voltage of VCO, Vinvco, it is the analog voltage generated from the Loop Filter if a Voltage Controlled Oscillator circuit is use in Phase Locked Loops (PLLs) systems.