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Power Minimization in IC Design: Principles and Applications
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 190 (28 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
Low Power Architectural Design Methodologies
 PH.D THESIS, MEMORANDUM NO. UCB/ERL M94/62, 30TH
, 1994
"... In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another de ..."
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Cited by 17 (0 self)
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In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom  and complexity  to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support lowpower system design. Lowpower techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and systemlevel optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the registertransfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switchlevel accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.
Low power multiplexer decomposition
 In International Symposium on Low Power Electronics and Design
, 1997
"... The advent of portable digital devices such as laptop personal computers has made low power circuit design an increasingly important research area. Recently, low poweT decomposition for simple logic gates such 0s AND and OR has been extensively researched. However, the problem of MUX decomposition ..."
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Cited by 9 (5 self)
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The advent of portable digital devices such as laptop personal computers has made low power circuit design an increasingly important research area. Recently, low poweT decomposition for simple logic gates such 0s AND and OR has been extensively researched. However, the problem of MUX decomposition to minimize power dissipation has not been addressed. In this paper, we study the pToblem of low power multiplexer (MUX) decomposition. MUX decomposition is the procedure of transforming an ntoone MUX into an equivalent tree of twotoone MUXes. We propose 0 formulation for the minimum power MUX decomposition problem based on the common CMOS pass transistor implementation of 0 MUX. Given the occurrence probabilities of the data signals and their on probabilities, we analyze the power dissipation of OUT MUX implementation and giue 0 general method for computing the power dissipation of 0 MUX tree decomposition. We then present several algorithms which eficiently generate minimum power MUX decompositions. We demonstrate the effectivene8s of our algorithms with experimental results. 1 Ihtroduction The advent of portable digital devices such as laptop personal computers has made low power circuit design an increasingly important research area. For example, portable electronic devices have limited battery life, and so the circuitry in these devices must be designed to dissipate as little power as possible without s,acrificing performance in terms of speed. Additionally, high power consumption increases the cost of handling heat dissipation and diminishes the reliabil
An Exact Gate Decomposition Algorithm for LowPower Technology Mapping
 in ICCAD
, 1997
"... With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implem ..."
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Cited by 8 (2 self)
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With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. In the literature, only heuristic algorithms are given for the lowpower gate decomposition problem. In this paper, we prove many properties an optimal decomposition tree must have. Based on these optimality properties, we design an efficient exact algorithm to solve the lowpower gate decomposition problem. Moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics. 1 Introduction With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. Power dissipation in digital CMOS circuits is dominat...
Optimal Low Power Technology Decomposition for a Linear Switching Model
"... The advent of portable digital devices such as laptop personal computers has made low power circuit design an increasingly important research area. In this paper we propose a new linear model of switching activities of logic gates. We demonstrate the usefulness of this model by applying it to the ..."
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The advent of portable digital devices such as laptop personal computers has made low power circuit design an increasingly important research area. In this paper we propose a new linear model of switching activities of logic gates. We demonstrate the usefulness of this model by applying it to the problem of technology decomposition for static CMOS logic. We provide an optimal algorithm for the technology decomposition problem under the new model, and conjecture that it is also optimal for the traditional nonlinear model. Finally, we demonstrate the effectiveness of our algorithms with strong experimental results.
On Switching Aware Synthesis for Combinational Circuits
"... Abstract. We propose a synthesis algorithm for combinational circuits which optimizes the expected number of gate switchings induced by typical sequences of input vectors. Our algorithm, which is based on simple observations concerning AND gates, performs quite well on sequences produced by the sam ..."
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Abstract. We propose a synthesis algorithm for combinational circuits which optimizes the expected number of gate switchings induced by typical sequences of input vectors. Our algorithm, which is based on simple observations concerning AND gates, performs quite well on sequences produced by the same probabilistic models used to generate the training sequences. 1
Node Normalization and Decomposition in Low Power Technology Mapping
"... In static CMOS technology the decomposition of the nodes of a circuit netlist can significantly reduce the overall power dissipation of the circuit. We present a normalization algorithm which extracts the largest recognizable nodes of the given structure. Then we examine a known decomposition algori ..."
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In static CMOS technology the decomposition of the nodes of a circuit netlist can significantly reduce the overall power dissipation of the circuit. We present a normalization algorithm which extracts the largest recognizable nodes of the given structure. Then we examine a known decomposition algorithm for the normalized nodes and propose a new one which is provable optimal and tractable for moderate node size. Resulting reduction of the overall switching activity on standard benchmark circuits is shown for ROBDD computed as well as uncorrelated signal probabilities.
MODELING AND SYNTHESIS OF COMBINATIONAL LOGIC CIRCUITS  A POWER DISSIPATION PERSPECTIVE
, 1998
"... With the advent of deep submicron technology, the number of transistors in a chip has increased very rapidly. As the complexity of VLSI circuits increases fast, the automation of the VLSI design has become very crucial not only to reduce design time and cost, but also to improve design quality. Th ..."
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With the advent of deep submicron technology, the number of transistors in a chip has increased very rapidly. As the complexity of VLSI circuits increases fast, the automation of the VLSI design has become very crucial not only to reduce design time and cost, but also to improve design quality. There are several criteria to measure design quality: area, delay, testabilityandpower consumption. Among them, the research is particularly focused on power consumption which is becoming more and more important with the advent of portable, highspeed, and highdensity devices. There are four problems addressed in this work. First, we develop an algorithm for automatic synthesis of combinational interface circuits while minimizing the area and the switching activity in the interface circuit. Secondly, we propose a new model for glitch analysis in logic circuits. This model is capable of modeling the generation, propagation and elimination of glitches in standard logic gates. Thirdly, we propose a new resynthesis algorithm for power reduction utilizing circuit symmetries. We propose an algorithm for detecting symmetries in a given circuit implementation
Exact Gate Decomposition for LowPower Technology Mapping
"... With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implem ..."
Abstract
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With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. In the literature, only heuristic algorithms are given for the lowpower gate decomposition problem. In this paper, we prove many properties an optimal decomposition tree must have. Based on these optimality properties, we design an efficient exact algorithm to solve the lowpower gate decomposition problem. Moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics. 1 Introduction With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. Power dissipation in digital CMOS circuits is dominate...