While the fault repair capability of Evolvable Hardware (EH) approaches have been previously demonstrated, further improvements to fault handling capability can be achieved by exploiting population diversity during all phases of the fault handling process. A new paradigm for online EH regeneration using Genetic Algorithms (GAs) called Consensus Based Evaluation (CBE) is developed where the performance of individuals is assessed based on broad consensus of the population instead of a conventional fitness function. Adoption of CBE enables information contained in the population to not only enrich the evolutionary process, but also support fault detection and isolation. On-line regeneration of functionality is achieved without additional test vectors by using the results of competitions between individuals in the population. Relative fitness measures support adaptation of the fitness evaluation procedure to support graceful degredation even in the presence of unpredictable changes in the operational environment, inputs, or the FPGA application. Application of CBE to FPGA-based multipliers demonstrates 100 % isolation of randomly injected stuck-at faults and evolution of a complete regeneration within 135 repair iterations while precluding the propagation of any discrepant output. The throughput of the system is maintained at 85.35 % throughout the repair process. 1

Run-time fault location in Field-Programmable Gate Arrays (FPGAs) is important because the resulting diagnostic information is used to reconfigure the FPGA for tolerating permanent faults. In order to minimize the system downtime and increase availability, a fault location technique with very short diagnostic latency is desired. In this paper, we present a fast approach for run-time FPGA fault location that can be used for high-availability reconfigurable systems. By integrating FPGA fault tolerance and Concurrent Error Detection (CED) techniques, our approach can achieve significant availability improvement by minimizing the number of reconfigurations required for FPGA fault location and recovery. The area overhead of our approach is studied and illustrated using applications implemented in FPGAs.

A method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. Discrepancy Mirrors provide coverage for the fault detector elements within the same mechanism used for the functional logic under test. The detector logic is self-testing and propagates functional outputs with adherence to a single fault-secure property so that erroneous outputs from any single fault are not propagated. Within the detector, bitwise equality comparisons are employed directly without additional data encoding/decoding schemes to determine the validity of the output. Fault handling is performed using the underlying data throughput so that additional test vectors are not required. The circuit was implemented for a Xilinx Virtex II Pro FPGA platform and fault-secure operation was verified using ModelSim-II for exhaustive stuck-at scenarios. Results indicate fault isolation in a pool of 100,000 resources using an expected value of 17.6 to 64.1 pairings when as little as one half of the inputs applied articulate the fault.

This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.

We discuss the problem of non-intrusive concurrent error detection (CED) for random logic. We analyze the optimal solution model and we point out the limitations that prevent logic synthesis from yielding a minimal cost implementation. We explain how duplication-based CED exploits decomposition to alleviate these limitations for the unrestricted error model. We then examine a compaction-based CED method, which employs a similar decomposition principle to alleviate synthesis limitations for restricted error models. We demonstrate the cost reduction achieved by the decomposed method through experimental results and we discuss the points where optimality is lost, possible remedies, and extension to finite state machines (FSMs). 1.

Abstract — Massively parallel “Processing-In-Memory” (PIM) architectures have been shown to yield increases in performance due to their “memory-centric ” nature. However, as PIM is still a developing technology, advanced issues such as error detection and failure recovery have not yet been addressed. We describe the application of concepts found in our multi-agent system, ADE, to PIM, incorporating its mechansims for automatic and intelligent error detection, failure recovery, and dynamic system reconfiguration in the PIM architecture, enhancing architecture robustness.

Concurrent error detection (CED) techniques are widely used to ensure data integrity in digital systems. Data integrity guarantees that the system outputs are either correct or an error is indicated when incorrect outputs are produced. This dissertation presents the results of theoretical and simulation studies of various CED techniques. The CED schemes studied are based on diverse duplication, simple duplication of identical implementations, and error-detection techniques like parity checking. The study aimed at (1) a quantitative comparison of the effectiveness of different CED schemes, and (2) developing design techniques for efficient concurrent error detection. A CED scheme based on diverse duplication compares the outputs of two different implementations of the same function and indicates an error when a mismatch occurs. The idea of such a CED technique is derived from the general concept of design diversity. The conventional notion of design diversity is qualitative and relies on independent generation of different implementations. In this dissertation, a metric to quantify design diversity is presented and used for analyzing CED schemes based on diverse duplication. A comparative study of different CED schemes by means of simulation experiments and theoretical analysis concludes that, in the worst-case, diverse duplication provides significantly better data integrity against multiple failures compared to other CED schemes. This result is especially significant in the context of Common-Mode Failures (CMFs). CMFs undermine the data integrity of any system with CED and belong to a special class of multiple failures whose probability of occurrence can be as high as that of single failures. New techniques and synthesis algorithms have been developed for the first time to efficiently design systems based on diverse duplication. New fault models for CMFs are proposed and the possible failure mechanisms for the modeled CMFs are analyzed. In addition, techniques for designing CED-based systems with guaranteed data integrity in the presence of modeled CMFs are described

We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits. We examine three different approaches for this purpose: (1) Identical state encoding of the two sequential logic implementations, duplication of flip-flops, diverse implementation of the combinational logic part (output logic and next-state logic) and comparators on flip-flop outputs and primary outputs; (2) Diverse state encoding of the two implementations, duplication of flipflops, diverse combinational logic implementation and comparators on primary outputs only; and (3) Identical state encoding, parity prediction for the flip-flops, diverse combinational logic implementation, comparators on primary outputs and parity checkers on flip-flop outputs. Our results for the simulated sequential benchmark circuits demonstrate that the third approach is most efficient in protecting sequential logic circuits against multiple and common-mode failures. The computational complexity of the data integrity analysis of the third approach is of the same order as that of the first approach and is at least an order of magnitude less than that of the second approach.

The paper focuses on error detection in circuits implemented in FPGAs using error detection codes (ED codes). The incorrect function of a given combinational circuit has to be detected and signalized at the time of its appearance and before its further distribution. It means that a safe operation is guaranteed. The ability to detect an error without stopping circuit function is called concurrent error detection (CED). We have used combinational circuits only to simplify testing process. A previous research was based on benchmarks described by tables. In some cases benchmarks with many inputs cannot be described by tables easily. The benchmarks used in our experiments to compute a quality of the code are described by equations. All of them will be implemented in XILINX FPGA circuits. Therefore the fault model considers the way of configuration data storage in memory. This work is a part of a more complex methodology of fault tolerant design based on FPGAs with a possibility to reconfigure the faulty part of the circuit. 1

New product development for safety-critical products is a challenging process, due to stringent quality and time-to-market requirements. In particular, such products undergo a certification process, prior to product market release. One of the bottlenecks of the design process for these products is the lack of commercially available EDA (Electronic Design Automation) tools, as this is a limited segment market.