A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle large-scale problems.

Excessive power supply noise can lead to overkill during delay test. A static compaction solution is described to prevent such overkill. Low-cost power supply noise models are developed and used in compaction. An error analysis of these models is given. This paper improves on prior work in terms of models and algorithm to increase accuracy and performance. Experimental results are given on ISCAS89 circuits. 1.

In this paper we give a brief overview of a heuristic method for approximately solving a statistical digital circuit sizing problem, by reducing it to a related deterministic sizing problem that includes extra margins in each of the gate delays to account for the variation. Since the method is based on solving a deterministic sizing problem, it readily handles large-scale problems. Numerical experiments show that the resulting designs are often substantially better than one in which the variation in delay is ignored, and often quite close to the global optimum. Moreover, the designs seem to be good despite the simplicity of the statistical model (which ignores gate distribution shape, correlations, and so on). We illustrate the method on a 32-bit Ladner-Fischer adder, with a simple resistor-capacitor (RC) delay model, and a Pelgrom model of delay variation.

Increasing parameter variations, high defect densities and a growing susceptibility to external noise in nanoscale technologies have led to a paradigm shift in design. Classical design strategies based on worst-case or average assumptions have been replaced by statistical design, and new robust and variation tolerant architectures have been developed. At the same time testing has become extremely challenging, as parameter variations may lead to an unacceptable behavior or change the impact of defects. Furthermore, for robust designs a precise quality assessment is required particularly showing the remaining robustness in the presence of manufacturing defects. The paper pinpoints the key challenges for testing nanoelectronic circuits in more detail, covering the range of variation-aware fault modeling via methods for statiscal testing and their algorithmic foundations to robustness analysis and quality binning.

gigascale, nano-meter devices, we see an increasing intersection of manufacturing test, design verification, and design for robustness. While each of these domains has its own unique failure modes and errors, we see a huge potential in shared solutions, especially in the following areas: 1. Delay testing and timing verification The noise-, process-, thermal- and power-induced delay variations make circuit delays much less predictable. At the same time, due to small and subtle defects, devices are more likely to marginally violate performance specifications under scaled technologies. Like the signal lines, clock lines are also becoming more susceptible to variations and defects. For timing verification, such trends invalidate traditional, static (i.e. vector-less) timing verification paradigms and create a demand for dynamic solutions that would require carefully crafted test vectors for accurate timing simulation. For delay testing, we need test vectors that can exercise various worst-case timing scenarios to screen out devices with parametric variations and small timing defects. To reduce the overall costs and effort involved in design and test, we need to develop models, tools, and methodologies that can generate high quality, cost-effective test vectors that serve both applications [1]. 2. Verification and test sharing the same computational technologies Some aspects of functional verification are now routinely performed with tools that employ ATPG and/or SAT techniques [2]. For example, establishing the equivalence between two implementations of the same design is now usually done using formal equivalence-checking tools, which have more or less replaced simulators as the preferred method. Such tools use ATPG, SAT and BDD engines, which are also widely used in tools for generating manufacturing tests [3]. Property verification via model checking, a technique which

To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defectoriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defectfree case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.

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This article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden.