Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for technologies below 100nm, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full custom implementation. Design reuse and analog synthesis make analog/RF design more a#ordable; however, the increasing process variability and lack of modeling accuracy remains extremely challenging for nanoscale analog/RF design. We propose an analog/RF circuit design methodology ORACLE, which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and applicationspecific variables. Concurrently, we demonstrate ORACLE for novel metal-mask configurable designs, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. We also include the silicon validation of the metal-mask configurable designs.

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First of all, I would like to express my sincere appreciation for my research advisor, Professor Ali Hajimiri, for his guidance and support over this five year journey. I would like to thank him for bringing me into the High-Speed Integrated Circuits Group at Caltech, where I have been able to work in my most favorite research field. Inspirations drawn from the fruitful and enlightening technical discussions with him have helped me overcome plenty of difficulties encountered in the design and experiments and have been crucial in making those projects successful. I am especially grateful for his constant encouragement, which will continue to promote my desire to do my best in my future career. I would like to thank Professor David Rutledge and Dr. Sander Weinreb. I have learned a lot in the technical discussions with them. Their valuable suggestions as well as support in providing test equipments in the Caltech Microwave Laboratory have appreciably accelerated the progress of my research projects. I feel very lucky to have worked with the current and previous members of Caltech

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this paper is an asymmetric adaptation of orthogonal frequency division multiplexing (OFDM). In a conventional OFDM system, the signal processing hardware is divided equally between the base station and the terminal. In the asymmetric system, most of the complex signal processing hardware is shifted to the base station, making the terminal a simpler and more power-efficient device. To send information to the base station, the terminal transmits a series of QPSK symbols that make up an OFDM-code. The code is designed to distribute the signal's energy into a number of OFDM sub-carriers which can be detected and combined within the base station's OFDM receiver. Other users transmit the same OFDM-codes within the same bandwidth and at the same time, but with slightly offset carrier frequencies. Because of the nature of OFDM, the codes from different users remain orthogonal, even with multipath dispersion. OFDM signals transmitted from the base station are detected at the terminal using a decimator-accumulator structure

Abstract—Long design cycles due to the inability to predict silicon realities are a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full-custom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remain extremely challenging for nanoscale analog/RF design. We propose a regular analog/RF IC using metal-mask configurability design methodology Optimization with Recourse of Analog Circuits including Layout Extraction (ORACLE), which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and application-specific variables. Furthermore, robust optimization is proposed to treat the design with variability problem, further enhancing the ORACLE methodology by providing yield bound for each configuration of regular designs. The statistical variations of the process parameters are captured by a confidence ellipsoid. We demonstrate ORACLE for regular Low Noise Amplifier designs using metal-mask configurability, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. Two RF oscillator design examples are shown to achieve robust designs with guaranteed yield bound. Index Terms—Configurable design, optimization with recourse, robustness, statistical optimization. I.

Monolithic RF circuits capable of operating over multiple frequency bands are highly desired due to popular demand for low cost and compact multiband radios. This thesis presents designs of one such RF circuit called LNA. The presented LNAs are frequency reconfigurable tuned amplifiers i.e. they are narrow band circuits whose frequency of operation can be dynamically changed. The frequency reconfigurability is achieved by the use of monolithic CMOS-MEMS passives. In this thesis all the possible configurations obtained by adding a single varactor to the input and the output of an emitter degenerated cascode LNA core has been analyzed. Low noise, low power, input match, frequency reconfigurability, and monolithic implementation were the main constraints to determine the acceptability of an configuration. Three acceptable configurations have been identified and circuit designs based on these configurations has been presented. Circuits have been designed using a methodology developed during this work. The methodology designs for good noise and power matching at the input, over the entire frequency range of operation, and under a DC power constraint.