Results 1  10
of
18
Zero Skew Clock Routing With Minimum Wirelength
, 1992
"... In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the ..."
Abstract

Cited by 73 (12 self)
 Add to MetaCart
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we first present the DeferredMerge Embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wirelength reduction over previous constructions in [17] [18]. The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. We also present a unified BB+DME algorithm, which constructs a clock tree t...
Reducing Clock Skew Variability via Cross Links
 IN PROCEEDINGS OF THE 41ST ANNUAL CONFERENCE ON DESIGN AUTOMATION
, 2004
"... Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular ..."
Abstract

Cited by 27 (6 self)
 Add to MetaCart
Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wires. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The e#ect of the link insertion on clock skew variability is analyzed. Based on the analysis, two link insertion schemes are proposed. These methods can quickly convert a clock tree to a nontree with significantly lower skew variability and very small amount of extra wires. Further, they can be applied to the recently popular nonzero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.
NonTree Routing
 IEEE Transactions on ComputerAided Design
, 1994
"... An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e., it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e., whe ..."
Abstract

Cited by 14 (2 self)
 Add to MetaCart
An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e., it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e., where cycles are admissible) . We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon. Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters. Finally, we observe that nontree routing also significantly reduces signal skew. 1 I...
A General Approach to Performance Analysis and Optimization of Asynchronous Circuits
, 1995
"... A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Indexpriority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships bet ..."
Abstract

Cited by 14 (0 self)
 Add to MetaCart
A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Indexpriority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships between all signal transitions in the circuit. Once these relationships are known, the circuit is then modeled as an extended eventrule system, which can be used to describe many circuits, including ones that are inherently disjunctive. An accurate indication of the performance of the circuit is obtained by analytically computing the period of the corresponding extended eventrule system.
Statistical based link insertion for robust clock network design,” ICCAD
 Proc. of the ICCAD
, 2005
"... We present a statistical based nontree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show ..."
Abstract

Cited by 7 (1 self)
 Add to MetaCart
We present a statistical based nontree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show that the robustness of the final clock network can be significantly improved with a small increase in wire length. 1
BDD decomposition for delay oriented pass transistor logic synthesis
 Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 13, Issue 8, Aug. 2005 Page(s):957
"... Abstract — We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the maxflow mincut techni ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
Abstract — We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the maxflow mincut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed implementations. Experimental results obtained by running our algorithm on the set of ISCAS’85 benchmarks show a 31 % improvement in delay and a 30 % improvement in area, on an average, as compared to static CMOS implementations for xor intensive circuits, while in case of arithmetic logic unit and control circuits that are nand intensive, improvements over static CMOS are small and inconsistent.
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
"... With the advent of sub100nm VLSI technologies, variation effects greatly increase the unwanted skew in Clock Distribution Networks (CDNs), thereby reducing the performance of the chip. Recent works on link based nontree CDN [1–4] propose crosslink insertion in a given clock tree to reduce skew va ..."
Abstract

Cited by 3 (3 self)
 Add to MetaCart
With the advent of sub100nm VLSI technologies, variation effects greatly increase the unwanted skew in Clock Distribution Networks (CDNs), thereby reducing the performance of the chip. Recent works on link based nontree CDN [1–4] propose crosslink insertion in a given clock tree to reduce skew variation. However, the current methods suffer from the drawback that they are empirical in nature, requiring the user to experiment with different parameter values. Also, the methods of [1–3] ignore the interaction between the different links while selecting the links for insertion. The method of [4] attempts to overcome this drawback using a statistical link insertion methodology. However, [4] is very slow even for relatively small circuits. In this paper, we propose a fast link insertion methodology which does not require selecting empirical parameters for link insertion. Our method also incrementally considers the effect of previously inserted links before choosing the next link. SPICE based Monte Carlo simulations show that our approach obtains comparable skew reduction to that of the existing approaches while drastically reducing the time taken to obtain a good linkbased nontree CDN. 1
Power Efficient TreeBased Crosslinks for Skew Reduction
"... Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variation ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of shortcircuit currents caused by multiple drivers in a nontree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered. Categories and Subject Descriptors B.7.m [Integrated Circuits]: Miscellaneous maintain balance. Nontree topologies vary from a tree with a limited number of additional crosslinks [9][12] to a complete mesh structure [5][8], where a crosslink is a wire segment that connects two tree nodes and a mesh is a set of crosslinks that connects all or a significant group of adjacent nodes within a specific level of a clock tree (see Figure 1). Mesh structures are designed to balance each of the clock delays at the leaves or at some intermediate level of the tree [5][8]. These topologies, however, increase the total wire length, resulting in higher capacitance and, consequently, significantly increased dynamic power consumption. Thus, power is traded off for skew. General Terms: Design Keywords: Nontree clock distribution network, clock tree,
GridtoPorts Clock Routing for High Performance Microprocessor Designs
"... Clock distribution in VLSI designs is of crucial importance and it is also a major source of power dissipation of a system. For today’s high performance microprocessors, clock signals are usually distributed by a global clock grid covering the whole chip, followed by postgrid routing that connects ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
Clock distribution in VLSI designs is of crucial importance and it is also a major source of power dissipation of a system. For today’s high performance microprocessors, clock signals are usually distributed by a global clock grid covering the whole chip, followed by postgrid routing that connects clock loads to the clock grid. Early study [7] shows that about 18.1 % of the total clock capacitance dissipation was due to this postgrid clock routing (i.e., lower mesh wires plus clock twig wires). This postgrid clock routing problem is thus an important one but not many previous works have addressed it. In this paper, we try to solve this problem of connecting clock ports to the clock grid through reserved tracks on multiple metal layers, with delay and slew constraints. Note that a set of routing tracks are reserved for this gridtoports clock wires in practice because of the conventional modular design style of highperformance microprocessors. We propose a new expansion algorithm based on the heap data structure to solve the problem effectively. Experimental results on industrial test cases show that our algorithm can improve over the latest work on this problem [10] significantly by reducing the capacitance by 24.6% and the wire length by 23.6%. We also validate our results using hspice simulation. Finally, our approach is very efficient and for larger test cases with about 2000 ports, the runtime is in seconds.