A bandlimited signal can be recovered from its periodic nonuniformly spaced samples provided the average sampling rate is at least the Nyquist rate. A multirate filter bank structure is used to both model this nonuniform sampling (through the analysis bank) and reconstruct a uniformly sampled sequence (through the synthesis bank). Several techniques for modelling the nonuniform sampling are presented for various cases of sampling. Conditions on the filter bank structure are used to accurately reconstruct uniform samples of the input signal at the Nyquist rate. Several examples and simulation results are presented, with emphasis on forms of nonuniform sampling that may be useful in mixed-signal integrated circuits.

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given.

Noise analysis and power distribution network reliability assessment is extremely important in deep sub-micron digital and mixed-signal circuit design. Both relate closely to the nonlinear loading impact of digital circuits. Consequently, accurate estimation of the latter is critical. In this paper, we present extraction techniques that automatically generate a family of small, time-varying macromodels for digital cell libraries, at the time of their library characterization. Our approach is based on importing and adapting the Time-Varying Padé (TVP) method, for linear time-varying (LTV) model reduction, from the mixed-signal macromodelling domain. Our approach features naturally higher accuracy than previous ones, and in addition, offers the user a tradeoff between accuracy and macromodel complexity. A key attraction of our approach is that it can be merged into cell library extraction methodologies to produce accurate-by-construction noise models for digital blocks. Simulations and comparisons confirming the efficacy of our approach are provided. I.

In the high performance integrated circuits phenomena like crosstalk, IR drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their consequences are assuming increasing dimensions compromising circuits functionality and not only their performances. This paper suggests a...

Abstract. The objective of this paper is to explore the applicability of a very specific design technique at a gate-level to achieve a reduction of switching noise in conventional CMOS digital circuits. The proposed technique optimizes switching noise maintaining operation speed, power consumption and transistor count. Basically, we will show how the selection of the suited pin in a gate for implementing a logic function, can bring important advantages in terms of switching noise reduction. The characterization of some CMOS 0.35 μm library cell shows different behavior regarding switching noise depending on what transitions in which input pin takes place. This has been used as the basis for a noise optimization methodology, verified through some design examples showing the noise reduction produced by the use of the proposed technique. 1

For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a Boundary Element Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to properly model any specific, layout-dependent doping patterns that are usually present in the top layers of the substrate, such as channel stop layers. This paper describes a way to incorporate these doping patterns into our substrate model by combining a BEM for the stratified doping profiles with a 2D FEM for the top-level, layout-dependent doping patterns, thereby achieving improved flexibility compared to BEM and improved speed compared to FEM. The method has been implemented in the SPACE layout to circuit extractor and it has been successfully verified with two other tools.

For modern integrated circuits, capacitive coupling effects between interconnects can play an important role. Also resistive coupling effects via the substrate may have a significant influence on circuit behavior. This has already been recognized some time ago [1], and several methods to model these effects have been developed [2]. In this paper we will show how we can model coupling effects that propagate through capacitances as well as through substrate resistances. We will describe a 3 dimensional model that allows to accurately and efficiently model these effects. It extends work that has previously been reported in [3] and [4]. We will give results that indicate that in some cases capacitive coupling effects via the substrate may severely degenerate circuit performance.

A method for reconstructing a bandlimited signal from its periodic bunched samples is presented. As in prior approaches, a multirate filter bank structure is used to reconstruct the signal; however, the technique used to design the reconstruction filter bank is different. The solution presented here employs an interpolation filter to model the signal at the input of the reconstruction filter bank. FIR synthesis filters are selected to reduce aliasing and distortions of the reconstructed signal. Simulation results showing the quality of reconstruction are presented. 1

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analog-to-digital converters on digital telecom ASICs Deliverable ICD-D1.4.2 Design case report about noise coupling analysis and reduction methodology Project: BANDIT ESPRIT 29260 Doc. Title: Intermediate design case report about noise coupling analysis and reduction methodology.