This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC tree model and the Elmore delay model. We decompose the routing tree for a multisource net into the source subtree (SST) and a set of loading subtrees (LSTs), and show that the optimal wiresizing solution satisfies a number of interesting properties, including: the LST separability, the LST monotone property, the SST local monotone property, and the dominance property. Furthermore, we study the optimal wiresizing problem using a variable segment-division rather than an a priori fixed segment-division as in all previous works and reveal the bundled refinement property. These properties lead to efficient algorithms to compute the optimal solutions. We have tested our algorithm on nets extracted from the multilayer layout for a high-performance Intel microprocessor. Accurate SPICE simulation shows that our methods reduce the average delay by up to 23.5% and the maximum delay by up to 37.8%, respectively, for the submicron CMOS technology when compared to the minimal wire width solution. In addition, the algorithm based on the variable segment-division yields a speedup of over 1003 time and does not lose any accuracy, when compared with the algorithm based on the a priori fixed segment-division

This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in addition to area and fringing capacitances. We introduce the formulation of symmetric and asymmetric wire sizing and spacing. We prove two important results on the symmetric and asymmetric effective-fringing properties which leadtoavery effective bound computation algorithm to compute the upper and lower bounds of the optimal wire sizing and spacing solution for all nets under consideration. Our experiments show that in most cases the upper and lower bounds meet quickly after a few iterations and we actually obtain the optimal solution. To our knowledge, this is the first in-depth study of global wire sizing and spacing for multiple nets with consideration of coupling capacitance. Experimental results show that our GISS solutions lead to substantial delay reduction than existing single net wire-sizing solutions without consideration of coupling capacitance.

In this paper, we consider the delay minimization problem of a wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three versions of the problem, namely using no buffer, using a given number of buffers, and using optimal number of buffers. We provide elegant closed form optimal solutions for all these versions.

This paper reports two sets of important results in our exploration of an interconnect-centric design methodology for deep submicron (DSM) designs: (I) We obtain a set of efficient, accurate performance and area estimation models for optimal wire sizing (OWS) using two simple wire sizing schemes, namely single-width sizing (1-WS) and two-width sizing (2-WS). These simple, efficient estimation models enable us to explore the trade-off between delay and area of interconnect designs. They also enable high level design tools to consider interconnect layout optimization during design planning. (II) Guided by our interconnect estimation models, we study the interconnect architecture planning problem for wire-width designs. We achieve a rather surprising result which suggests that two pre-determined wire widths per metal layer are sufficient to achieve near-optimal performance for current and future technologies from 0.25m to 0.07m generations.. This result will greatly simplify the routing architecture and routing tools for DSM designs. We believe that our interconnect estimation and planning results will have a significant impact to guide high-performance DSM designs.

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This paper presents a set of interconnect performance estimation models for design planning with consideration of various effective interconnect layout optimization techniques, including optimal wire sizing, simultaneous driver and wire sizing, and simultaneous buffer insertion/sizing and wire sizing. These models are extremely efficient, yet provide high degree of accuracy. They have been tested on a wide range of parameters and shown to have over 90% accuracy on average compared to running best-available interconnect layout optimization algorithms directly. As a result, these fast yet accurate models can be used efficiently during high-level design space exploration, interconnect-driven design planning/synthesis, and timing-driven placement to ensure design convergence for deep submicrometer designs.

In this paper, we consider non-uniform wire-sizing under the Elmore delay model. Given a wiresegment of length L, let f#x# be the width of the wireatposition x, 0 # x #L. It was shown in #2, 5# that the optimal wire-sizing function which minimizes delay is an exponential tapering function f#x#=ae ,bx , where a#0and b#0areconstants. Unfortunately, #2, 5# did not consider fringing capacitance which is at least comparable in size to areacapacitancein deep submircon designs. As a result, exponential tapering is no longer the optimal strategy. In this paper, we show that the optimal wire-sizing function, taking fringing capacitance into consideration, is f#x#= ,c f 2c 0 # 1 W# ,c f ae ,bx # +1# where W#x#= P 1 n=1 #,n# n,1 n! x n is the Lambert's W function, cf and c0 are the respective fringing capacitance and areacapacitance of wireper unit square, a#0and b#0areconstants. The optimal wire-sizing function degenerates into an exponential tapering function as cf...

We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area subject to sink-delay bounds; and 3) maximum sinkdelay. We first present an algorithm NWSA-wd for minimizing total weighted sink-delays based on iteratively applying the wire-sizing formula in [1]. We show that NWSA-wd always converges to an optimal wire-sizing solution. Based on NWSA-wd and the Lagrangian relaxation technique, we obtained two algorithms NWSA-db and NWSA-md which can optimally solve the other two minimization objectives. Experimental results show that our algorithms are efficient both in terms of runtime and storage. For example, NWSAwd, with linear runtime and storage, can solve a 6201-wiresegment routing-tree problem using about 1.5-second runtime and 1.3-MB memory on an IBM RS/6000 workstation. 1 Introduction As VLSI technology continues to scale down, interconnect delay has become the d...

Abstract- This paper presents the analysis and modeling of the nonuniform substrate temperature in high performance ICs and its effect on the integrity of the clock signal. Using a novel non-uniform temperature-dependent distributed RC interconnect delay model, the behavior of clock skew in presence of the substrate thermal gradients is analyzed and some design guidelines are provided to ensure the integrity of the clock signal. I.