We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal trade-o s among competing performance measures such aspower, open-loop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal trade-o curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a

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Until recently, verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became now feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time, when applied to the class of Wallace-tree like multipliers.

We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higher-order terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuck-at faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuck-at faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuck-at faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuck-at fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...

Abstract-We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.

In this paper we present a new model for diagnosis of errors in Synchronous Sequential Circuits (SCC) on the functional level. In contrast to many previously published approaches we do not consider a specific implementation. Instead we use tests based on the transition behavior of the corresponding Finite State Machine (FSM). Thus, the approach can be used for verification and test. We describe a method for constructing a minimal cost test based on AND/OR graphs. Exact and heuristic methods are presented. First experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Nowadays, circuit design is becoming more and more complex. Thus, the error probability also increases. Since time-to-market aspects are increasingly important it is desirable to detect errors as early as possible. Additionally, this also reduces the production costs. For this, nowadays CAD tools should also support features for error diagnosis, i.e. error...

In this paper we present a model for diagnosis of errors in Sequential Multi-Valued Logic Networks (SMVLN). The method allows not only to detect errors in an implementation, but also identifies the fault location. In contrast to many previously presented approaches this model does not consider a specific implementation. Instead the model assumes tests based on the transition behavior of the corresponding MVL Finite State Machine (FSM) on the functional level. We present a method for constructing a minimal cost test based on AND/OR graphs using tests with MV outcomes. The model enables encoding over twovalued circuits as well as consideration of SMVLNs. The new approach provides efficient solution even for large MVL FSMs with up to 50000 states. Experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Several circuit design methods for Multi-Valued Logic (MVL) have been proposed in the past few years [3, 6]. These new ...