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Identifying Sequentially Untestable Faults Using Illegal States
 In Proc. of the VLSI Test Symposium
, 1995
"... This paper addresses the problem of identifying untestable faults in synchronous sequential circuits without assuming a global reset mechanism. First, we present an efficient algorithm to identify illegal states in the circuit. An important feature of this algorithm is its functional partitioning, w ..."
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Cited by 12 (1 self)
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This paper addresses the problem of identifying untestable faults in synchronous sequential circuits without assuming a global reset mechanism. First, we present an efficient algorithm to identify illegal states in the circuit. An important feature of this algorithm is its functional partitioning, which results in efficient processing of large circuits. The algorithm incrementally builds the set of illegal states which allows it to obtain partial solutions in situations when the search must be curtailed due to resource limitations. No illegal states will be found in such situations by the forward search used in previous methods. Next, we present an algorithm that uses these illegal states to find sequentially untestable faults without exhaustive search. This is unlike all previous methods that rely on automatic test pattern generation (ATPG), which results in very large computational requirements. Our experimental results on benchmark circuits indicate that we find a large number of un...
On Random Pattern Generation with the Selfish Gene Algorithm for Testing
 Digital Sequential Circuits,” in Proc. International Test Conf
, 2004
"... A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. We enhance the spectral method of sequential circuit test generation by using a SG algorithm. The objects ..."
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Cited by 10 (7 self)
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A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. We enhance the spectral method of sequential circuit test generation by using a SG algorithm. The objects of evolution are the Hadamard spectral matrix, nonlinear digital signal processing (DSP) filtering cutoff values, vector holding time, and relative input phase shifts, which are all modeled as genes. These characteristics, extracted from compacted test vectors, are used to create new vector sequences to be further compacted with higher fault coverage. Alternatively, new vectors were generated by holding randomly selected vectors and then randomly perturbing some bits in 8bit chunks of bit streams. Both the SG algorithm and holding with bitperturbation can outperform the previouslypublished spectral method in either fault coverage, or shorter vector length, or both. The SG algorithm is often superior to random bitperturbation but it requires more CPU time. 1
Functional test generation for synchronous sequential circuits
 IEEE Trans. on CAD/ICAS
, 1996
"... AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these test ..."
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Cited by 2 (0 self)
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AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cubebased test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of timeframes and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gatelevel stuck faults that is higher than a gatelevel sequentialcircuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementationindependent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.
Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation
"... A new method is proposed for checking the equivalence of two irredundant logic implementations of a combinational Boolean function. The procedure consists of generation of complete checkpoint fault test sets for both circuits. The two test sets are concatenated and both circuits are simulated to obt ..."
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A new method is proposed for checking the equivalence of two irredundant logic implementations of a combinational Boolean function. The procedure consists of generation of complete checkpoint fault test sets for both circuits. The two test sets are concatenated and both circuits are simulated to obtain the response to the combined test set. If the responses of the two circuits match for all vectors, then they are declared to be equivalent. We examine a case where this heuristic fails. In such cases, the use of fault simulation is shown to discover nonequivalence even when the two circuits produce the same output. We prove that if the two circuits were different, then some faults on the primary inputs of a composite equivalence checking circuit must be detectable. Using the simulation of single stuckat faults at the primary inputs of that circuit, the new heuristic recommends the use of a vector set in which the Hamming distance between any two vectors does not exceed 3. 1.