We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most n + 3 modeling gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuckat fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridgingfault modeling, diagnosis, circuit optimization, and testing of multiply-testable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partial-scan circuits in which some lines are split, leading to a transformation of single stuck-at faults into multiple faults. 1.

Abstract-We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.

A collection of fast algorithms for generating test vectors for PLAs is presented and analyzed. It is shown that, in some sense, complete sets of test vectors for almost all such circuits which are irredundant, primal, and non-tautological can be generated quickly. 1 Introduction It has been known for some time that logic optimization can produce circuits that are completely testable for all stuck-at faults. The relationship between testability and Boolean minimization for two-level combinational circuits dates back to the Quine-McCluskey algorithm [8]. The notions of primality and irredundancy were generalized for multi-level circuits in [1]. Recent work in synthesis for testability has been able to ensure complete multiple-fault testability for multi-level combinational logic circuits [5]. All of these results only show in varying ways that with unlimited computational resources test vectors could be generated for all stuck-at faults in a circuit; however, in practice the testabilit...

Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations (D 1;1;2 [9], extraction, DeMorgan) which was proved to keep 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the followi...