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Multiple Faults: Modeling, Simulation and Test
, 2002
"... We give an algorithm to model any given multiple stuckat fault as a single stuckat fault. The procedure requires insertion of at most n + 3 modeling gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the ..."
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Cited by 6 (3 self)
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We give an algorithm to model any given multiple stuckat fault as a single stuckat fault. The procedure requires insertion of at most n + 3 modeling gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuckat fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridgingfault modeling, diagnosis, circuit optimization, and testing of multiplytestable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partialscan circuits in which some lines are split, leading to a transformation of single stuckat faults into multiple faults. 1.
On the Generation of Test Patterns for Multiple Faults
 J. Electronic Testing: Theory and Applic
, 1993
"... This paper presents a new method to generate test patterns for multiple stuckat faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multip ..."
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Cited by 2 (0 self)
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This paper presents a new method to generate test patterns for multiple stuckat faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in the FAN and SOCRATES algorithms to guide the search part of the algorithm and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuckat faults.
Functional test generation for synchronous sequential circuits
 IEEE Trans. on CAD/ICAS
, 1996
"... AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these test ..."
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Cited by 2 (0 self)
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AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cubebased test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of timeframes and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gatelevel stuck faults that is higher than a gatelevel sequentialcircuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementationindependent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.
Probabilistic Analysis of Algorithms for Stuckat Test Generation in PLAs
 Lecture Notes in Control and Information Sciences 174
, 1995
"... A collection of fast algorithms for generating test vectors for PLAs is presented and analyzed. It is shown that, in some sense, complete sets of test vectors for almost all such circuits which are irredundant, primal, and nontautological can be generated quickly. 1 Introduction It has been known ..."
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Cited by 1 (1 self)
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A collection of fast algorithms for generating test vectors for PLAs is presented and analyzed. It is shown that, in some sense, complete sets of test vectors for almost all such circuits which are irredundant, primal, and nontautological can be generated quickly. 1 Introduction It has been known for some time that logic optimization can produce circuits that are completely testable for all stuckat faults. The relationship between testability and Boolean minimization for twolevel combinational circuits dates back to the QuineMcCluskey algorithm [8]. The notions of primality and irredundancy were generalized for multilevel circuits in [1]. Recent work in synthesis for testability has been able to ensure complete multiplefault testability for multilevel combinational logic circuits [5]. All of these results only show in varying ways that with unlimited computational resources test vectors could be generated for all stuckat faults in a circuit; however, in practice the testabilit...
Multiple Faults: Modeling, Simulation and Test £
"... We give an algorithm to model any given multiple stuckat fault as a single stuckat fault. The procedure requires insertion of at most Ò modeling gates, when the multiplicity of the targeted fault is Ò. We prove that the modeled circuit is functionally equivalent to the original circuit and the tar ..."
Abstract
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We give an algorithm to model any given multiple stuckat fault as a single stuckat fault. The procedure requires insertion of at most Ò modeling gates, when the multiplicity of the targeted fault is Ò. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuckat fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridgingfault modeling, diagnosis, circuit optimization, and testing of multiplytestable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partialscan circuits in which some lines are split, leading to a transformation of single stuckat faults into multiple faults. 1.
Exploring Relationships Among Several Testabilities
"... Singlefault, multifault, 01 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fa ..."
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Singlefault, multifault, 01 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 01 static sensitizability are equivalent in twolevel singleoutput circuits. We have also proved that 100% 01 static sensitizability implies 100% multifault testability, and that 100% robust path delay fault testability implies 100% multifault testability in twolevel circuits. Several new conditions for gate merging while keeping 100% singlefault testability are presented. We further proved that the three transformations (D 1;1;2 [9], extraction, DeMorgan) which was proved to keep 100% single fault testability also preserve 100% multiplefault testability, 100% multifault testability, 100% robust path delay fault testability. We have answered the followi...