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Deterministic Pattern Generation for Weighted Random Pattern Testing
 Proc. of European Design & Test Conference
, 1996
"... Weighted random pattern testing is now widely accepted as a very economic way for external testing as well as for implementing a builtin selftest (BIST) scheme. The weights may be computed either by structural analysis or by extracting the required information from a precomputed deterministic ..."
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Weighted random pattern testing is now widely accepted as a very economic way for external testing as well as for implementing a builtin selftest (BIST) scheme. The weights may be computed either by structural analysis or by extracting the required information from a precomputed deterministic test set. In this paper, we present a method for generating deterministic test patterns which can easily be transformed into weight sets. These test patterns contain only minimal redundant information such that the weight generation process is not biased, and the patterns are grouped such that the conflicts within a group are minimized. The quality of the weight sets obtained this way is superior to the approaches published so far with respect to a small number of weights and weighted patterns, and a complete fault coverage for all the ISCAS85 and ISCAS89 benchmark circuits. 1. Introduction Various BIST architectures based on pseudoexhaustive, random, weighted random, and de...
The PseudoExhaustive Test of Sequential Circuits
, 1992
"... The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhau ..."
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The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the presented test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the wellknown benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation.
Functional test generation for synchronous sequential circuits
 IEEE Trans. on CAD/ICAS
, 1996
"... AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these test ..."
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AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cubebased test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of timeframes and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gatelevel stuck faults that is higher than a gatelevel sequentialcircuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementationindependent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.
Bounds on Pseudoexhaustive Test Length
 IEEE Trans. On VLSI
, 1998
"... Abstract—Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (coneindependent) and circuitspecific (conedependent) bounds on the minimal length of a test r ..."
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Abstract—Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (coneindependent) and circuitspecific (conedependent) bounds on the minimal length of a test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and where each output has � or fewer inputs, we show that the circuit can always be pseudoexhaustively tested with just P � patterns. We derive a tight upper bound on pseudoexhaustive test length for a given circuit by utilizing the knowledge of the structure of the circuit output cones. Since our circuitspecific bound is sensitive to the ordering of the circuit inputs, we show how the bound can be improved by permuting these inputs. Index Terms — LFSR, pseudoexhaustive testing, test length bound.
A Tool for Examining the Behaviour of Faults and Errors in Software Revision
, 2000
"... This report describes the Propagation Analysis Environment (PROPANE) which is a desktop environment for conducting experiments with error injection and fault injection in order to analyse the propagation and effects of errors and faults in software systems. PROPANE supports the injection of a variet ..."
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This report describes the Propagation Analysis Environment (PROPANE) which is a desktop environment for conducting experiments with error injection and fault injection in order to analyse the propagation and effects of errors and faults in software systems. PROPANE supports the injection of a variety of errors types into variables of a software system, as well as controlled injection of faults (by mutation of the source code). PROPANE also has support for various types of probes that can be used to log the values of variables and the occurrences of events during software execution. PROPANE is mainly aimed at, and was specifically developed for the analysis and evaluation of software for single node embedded control systems, although due to its general nature it may be used in many other areas.