Abstract- The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electro-thermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. In difference to other known simulator couplings a time step algorithm is used. Its implementation into simulation tools is described. The thermal modeling of the die/package structure and the extended modeling of the electronic circuit is discussed. Simulation results which indicate the capabilities of the methodology for electrothermal simulation are compared to experimental results. Index Terms- Analog modeling with behavioral languages, circuit simulation, electro-thermal circuit simulation, finite element simulation, simulator coupling, thermal modeling. I.

Several methods are presented for highly efficient calculation of substrate noise transport in integrated circuits. A three-dimensional Green's function-based boundary element method, accelerated through use of the fast Fourier transform, allows the computation of sensitivities with respect to all substrate parameters at a considerably higher speed than any methods reported in the literature. Substrate sensitivities are used in a number of physical optimization tools, such as placement and trend analysis. The aim is a fast and accurate estimation of the impact of technology migration and/or layout redesign on substrate noise and, ultimately, on the circuit's overall performance. The suitability of the approach is shown through industrial-strength mixed-mode integrated circuits fabricated on a standard CMOS process.

Abstract — A methodology is proposed to improve the efficiency of the substrate impedance extraction process for a large scale circuit by exploiting the circuit activity. Similarly biased regions of the substrate short-circuited by the ground network are identified to reduce the computational complexity of the extraction process. Each of these voltage domains is represented by a single equivalent input port to the substrate, merging the remaining ports within that domain. An algorithm is presented to determine these domains and generate an equivalent port for each domain. The parasitic impedance of the ground network is updated to maintain accuracy. A reduction of more than two orders of magnitude in the number of extracted substrate resistances is demonstrated while introducing 15 % error in the rms value of the substrate noise voltage at the sense node. I.

Abstract—A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%. Index Terms—Ground noise, high level analysis methodology, mixed-signal ICs, substrate coupling noise, substrate extraction, substrate noise analysis. I.

engineering.

A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution network of an aggressor circuit are exploited to reduce the overall number of input ports before the substrate extraction process. Specifically, the substrate of an aggressor circuit is partitioned into voltage domains where each domain is represented by a single substrate contact. The remaining ports of the substrate within that domain are ignored to reduce the computational complexity. A linear time algorithm is developed to identify these voltage domains and generate an equivalent contact. A reduction of more than four orders of magnitude in the number of extracted substrate resistances is demonstrated while introducing 20 % error in the peak-to-peak value of the substrate noise voltage. Categories and Subject Descriptors B.7.m [Integrated Circuits]: Miscellaneous—Mixed signal circuits, substrate coupling noise, noise analysis