: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. 1.0 Introduction With much of research efforts of the past ten years directed toward increasing the speed of digital systems, present-day technologies possess computing capabilities which make possible powerful personal workstations, sophisticated computer graphics, and multi-media capabilities such as real-time speech recognition and...

Current High Level Synthesis methodologies are based on synthesis algorithms that take a behavioural description of a circuit and schedules the datapath operations over the available time in order to reuse the components in the datapath that have been selected to implement the functionality. However, although the synthesis algorithms are general and produce acceptable solutions on regular structures, the generality of the synthesis algorithms usually results in poor quality designs. The Enhanced Allocation Rule Language Interpreter (EARLI) was designed especially with the intent of improving the synthesis of regular datapath structures in mind. EARLI tries to improve the structure, given in the form of a behavioural CDFG, of a design and tries to implement it as optimal as possible by applying optimising design transformations. The design transformations are specified as rules in a pattern and transformation language. After transformation, a simple ALAP-schedule can be performed instea...