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An Analog Memory Circuit for Spiking Silicon Neurons
, 1997
"... this paper, the simplest to understand is the CAPSandDAC, whose basic architecture is shown in Fig. 1a. The voltage on any one capacitor is precisely set by a digitaltoanalog converter (DAC) and demultiplexer. Address lines select the memory location to be set, and data lines to the DAC encode ..."
Abstract

Cited by 7 (1 self)
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this paper, the simplest to understand is the CAPSandDAC, whose basic architecture is shown in Fig. 1a. The voltage on any one capacitor is precisely set by a digitaltoanalog converter (DAC) and demultiplexer. Address lines select the memory location to be set, and data lines to the DAC encode the desired voltage. Since there are unavoidable leakage paths, the voltage of each memory must be refreshed periodically by using digitally encoded states, which are stored, typically, offchip in conventional digital memory (SRAM or DRAM). The demultiplexer circuitry would normally be integrated along with the capacitor array but the DAC could be located off chip to save space and reduce pin count. The rate of voltage decay due to charge leakage in CAPSandDAC memory depends on temperature, leakage pathway characteristics, and the capacity of each capacitor. The decay rate measured as a percentage of initial state is, to first order, independent of initial voltage. Therefore, to maintain state to a certain precision requires that refreshing occurs frequently enough to keep the associated voltage ripple, expressed as a binary fraction of the full scale swing, less than 0.5 of a least significant bit (LSB). If we assume the decay is a single exponential then the refresh frequency 3