This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models. A key contribution is a new algorithm for determining analog testability. Experimentally, we determined the testability and faults of a fabricated 10 bit digital-to-analog converter modeled using the analog hardware description language, Cadence-AHDL. Also, we applied the testability analysis at the circuit level using SPICE sensitivity analysis. 1 Introduction The goal for testability and fault diagnosis is to identify fault location and severity from measurements. By identifying the faults, we can identify design weak spots and problems in processing, thus pinpointing the critical areas for improvement in the next design iteration. In this context, the testability of a circuit corresponds to the extent faults can be identified from measurements. Fault diagnosis corresponds to the algorithm for computing the severity of faults from measurements. In gene...