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Feasibility and Performance Region Modeling of Analog and Digital Circuits
- Analog Integrated Circuits and Signal Processing
, 1996
"... Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology ..."
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Cited by 11 (0 self)
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Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is ...
Simulating the impact of pattern-dependent poly-CD variation on circuit performance
- Proc. IEEE Vol. 11 #4, Transactions on Semiconductor Manufacturing
, 1998
"... Abstract—In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 "m 642 8 SRAM macrocell layout. For this example, the impact as measured throu ..."
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Cited by 6 (1 self)
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Abstract—In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 "m 642 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell. I.
Feasibility Region Modeling of Analog Circuits for Hierarchical Circuit Design
- in IEEE MWSCS
, 1994
"... During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-bloc ..."
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Cited by 2 (2 self)
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During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy. 1 Hierarchical Circuit Design An increasing percentage of IC's have analog circuit designs in them. These and other requirements stress the need for automatic synthesis tools for analog circuits. Hierarchy plays a significant role in the design of digital and analog circuits. A large design can be broken up into smaller sub-blocks at the different levels of a hierarchy. An example hierarchy for an A/D converter ...

