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25
On the False Path Problem in Hard RealTime Programs
 In Proceedings of the 8th Euromicro Workshop on Realtime Systems
, 1996
"... This paper addresses the important subject of estimating the worstcase execution time (WCET) of hard realtime programs essentially needed for further evaluation of realtime systems. Purely structure oriented methods, analysing the control flow of the program without taking into account functional ..."
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Cited by 64 (9 self)
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This paper addresses the important subject of estimating the worstcase execution time (WCET) of hard realtime programs essentially needed for further evaluation of realtime systems. Purely structure oriented methods, analysing the control flow of the program without taking into account functional dependencies, tend to overestimate the execution time. An exact solution of this NPcomplete problem is impossible for larger applications. In this paper, we propose a new heuristic of finding an estimate on the WCET. It provides a reasonable tradeoff between analysis results and analysis efforts: the results will still be better than purely structure oriented methods without spending too much time on finding an exact solution. For this purpose our approach does not need any user annotations except for maximum loop counts and maximum recursion depths. The actual algorithm combines pruned path enumeration with the concept of symbolic execution. 1. Introduction Predicting the execution times...
Fast statistical timing analysis handling arbitrary delay correlations
 in Proc. IEEE/ACM Design Autom. Conf
"... An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire cumulative distribution function of the circuit delay using a new mathematical formulation. Spatial as well as structural c ..."
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Cited by 42 (3 self)
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An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire cumulative distribution function of the circuit delay using a new mathematical formulation. Spatial as well as structural correlations between gate and wire delays can be taken into account. The algorithm can handle node delays described by nonGaussian distributions. Because the analytical computation of an exact cumulative distribution function for a probabilistic graph with arbitrary distributions is infeasible, we find tight upper and lower bounds on the true cumulative distribution. An efficient algorithm to compute the bounds is based on a PERTlike single traversal of the subgraph containing the set of N deterministically longest paths. The efficiency and accuracy of the algorithm is demonstrated on a set of ISCAS’85 benchmarks. Across all the benchmarks, the average rms error between the exact distribution and lower bound is 0.7%, and the average maximum error at 95 th percentile is 0.6%. The computation of bounds for the largest benchmark takes 39 seconds.
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 16 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
Nearcritical path analysis of program activity graphs
 Proceedings of the 2nd International Workshop on Modeling, Analysis, and Simulation on Computer and Telecommunications Systems
, 1994
"... ..."
Distributed Eventdriven Simulation: Scheduling Strategies and Resource Management
, 2000
"... Optimistic parallel discrete event simulation method is applied to large scale data parallel applications. Specificly, optimizations for state saving of large state vectors and bounded optimism are incorporated in the simulation environment. Dynamic load balancing is studied, and a checkpoint and mi ..."
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Cited by 7 (1 self)
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Optimistic parallel discrete event simulation method is applied to large scale data parallel applications. Specificly, optimizations for state saving of large state vectors and bounded optimism are incorporated in the simulation environment. Dynamic load balancing is studied, and a checkpoint and migration mechanism is implemented and integrated with the PVM message passing environment.
Delay and Area Optimization for Compact Placement by Gate Resizing and Relocation
 Proc. Intl. Conf. on CAD
, 1994
"... In this paper, we rst present an e cient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure isembedded within the placemen ..."
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Cited by 4 (0 self)
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In this paper, we rst present an e cient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure isembedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As aresult, the algorithm is able to obtain superior solutions. 1
On Performance and Area Optimization of VLSI Systems Using Genetic Algorithms
 VLSI Design
, 1995
"... A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. ..."
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Cited by 3 (0 self)
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A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, nonRC based transistor delay model was used which resulted in a nonconvex relationship between the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete, nonconvex, nonlinear optimization problems than traditional calculusbased algorithms. By using the genetic algorithms in the performance and area optimization, we are able to find the optimal values for both delay and silicon area for the ISCAS benchmark circuits. Key Words: Area and Performance optimization; Transistor Sizing; Genetic algorithms 1 Introduction The techniques for performance and area optimization of VLSI systems can be divi...
Optimal Project Planning Through Feasible Path Analysis
, 1996
"... In this paper we present a powerful technique for analysing production networks in the presence of decisionmaking variables and cost flexibility. Processes are modelled as a network, similar to PERT/CPM schemes, but with builtin decision and cost variables. For minimal increased complexity in the ..."
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Cited by 1 (1 self)
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In this paper we present a powerful technique for analysing production networks in the presence of decisionmaking variables and cost flexibility. Processes are modelled as a network, similar to PERT/CPM schemes, but with builtin decision and cost variables. For minimal increased complexity in the development of the network, we show that powerful analysis and optimisation techniques are enabled. The concept of feasible paths is introduced as a key factor in the analysis and optimisation process. 1 INTRODUCTION Networkbased approaches, particularly techniques such as PERT/CPM, are still widely used for planning and control of large projects [1] [3] [9]. They are effective at showing the interrelationships of combined activities, and can allow approximations of processing times and critical paths in the project. However, they are poorly suited for modelling the interdependence of the many decisions which must be made during the project  even though the general "rules" for many decisi...
Timing Optimization By Gate Resizing And Critical Path Identification
 IEEE trans. On CAD of Integrated Circuits and Systems
, 1995
"... Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a majo ..."
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Cited by 1 (0 self)
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Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control the hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM [1], called PODEM, ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitely reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing. 1 1. Introduction In recent years, semiconductor technology h...