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30
Checkpointing and its applications
 IEEE, IEEE Computer Society
, 1995
"... Is the Framingham coronary heart disease absolute risk function ..."
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Cited by 84 (8 self)
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Is the Framingham coronary heart disease absolute risk function
Simulation and optimization of the power distribution network
 in VLSI circuits,” in Proc. Int. Conf. Comput.Aided Des
"... In this paper, we present simulation techniques to estimate the worstcase voltage variation using a RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequencydomain steadystate simulation of the linear RC ci ..."
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Cited by 20 (0 self)
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In this paper, we present simulation techniques to estimate the worstcase voltage variation using a RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequencydomain steadystate simulation of the linear RC circuit to evaluate the worstcase instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequencydomain and timedomain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques. 1
Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm
 Proceedings of IEEE 1997 Custom Integrated Circuits Conference
, 1997
"... We present a geneticalgorithmbased approach for estimating the maximum power dissipation and instantaneous current through supply lines for CMOS circuits. Our approach can handle large combinational and sequential circuits with arbitrary but known delays. To obtain accurate results we extract the ..."
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Cited by 20 (8 self)
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We present a geneticalgorithmbased approach for estimating the maximum power dissipation and instantaneous current through supply lines for CMOS circuits. Our approach can handle large combinational and sequential circuits with arbitrary but known delays. To obtain accurate results we extract the timing and current information from transistorlevel and generaldelay gatelevel simulation. Our experimental results show that the patterns generated by our approach produce on the average a lower bound on the maximum power which is 41% tighter than the one obtained by weighted random patterns for estimating the maximum power. Also, our lower bound for the maximum instantaneous current is 21% tighter as compared to the weighted random patterns. 1. Introduction With increasing demands for high reliability in modern VLSI designs, accurate estimation of the maximum power dissipation and maximum instantaneous current during the design process is becoming essential. Excessive power dissipatio...
Power Estimation Techniques for Integrated Circuits
, 1995
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a co ..."
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Cited by 18 (0 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e longterm behavior of logic signals wit I! probabilities. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.
Congestionaware topology optimization of structured power/ground networks
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
"... This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connect ..."
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Cited by 17 (4 self)
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This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connected to each other enables the use of a hierarchical circuit analysis approach to identify the tiles containing the nodes having the greatest drops. Starting from an initial equal number of wires in each of the rectangular tiles, wires are added in the tiles using an iterative sensitivity based optimizer. A novel and efficient table lookup scheme is employed to provide gradient information to the optimizer. Experimental results on test circuits of practical chip sizes show that the proposed P/G network topology after optimization saves 16 % to 28 % of the chip wiring area over other commonly used topologies.
A stochastic approach to power grid analysis
 in Proc. ACM/IEEE DAC
, 2004
"... Power supply integrity analysis is critical in modern high performance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are mo ..."
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Cited by 14 (0 self)
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Power supply integrity analysis is critical in modern high performance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical information is extracted, including correlation information between blocks in both space and time. We then propose a method to propagate the statistical parameters of the block currents through the linear model of the power grid to obtain the mean and standard deviation of the voltage drops at any node in the grid. We show that the run time is linear with the length of the current waveforms allowing for extensive vectors, up to millions of cycles, to be analyzed. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its accuracy and efficiency. The proposed statistical analysis can be use to determine which portions of the grid are most likely to fail as well as to provide information for other analyses, such as statistical timing analysis.
Estimation of maximum power supply noise for deep submicron designs
 in Proc. of ISLPED
, 1998
"... We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep submicron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and ..."
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Cited by 13 (7 self)
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We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep submicron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells ’ current and voltage libraries, the power supply noise of a 2vector sequence can be estimated efficiently by a celllevel waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise. 1.
Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Circuits
 in VLSI Circuits”, Proceedings of Design Automation Conference
, 1997
"... This paper proposes to use quantile points of the cumulative distribution function for powerconsumption to provide detailed information about the powerdistribution in a circuit. Thepaper also presents two techniquesbasedon population pruning and stratification to improve the efficiency of estimation ..."
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Cited by 11 (4 self)
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This paper proposes to use quantile points of the cumulative distribution function for powerconsumption to provide detailed information about the powerdistribution in a circuit. Thepaper also presents two techniquesbasedon population pruning and stratification to improve the efficiency of estimation. Both population pruningand stratification are basedon a low cost predictor, such as zerodelay power estimate. Experimental results show the effectiveness of the proposed techniques in providing detailed power distribution information. 1 Introduction In the past, average and peak power dissipations have been the primary focus of power estimation techniques and tools. It has however become important to estimate the power distribution of the circuit over a large number of clock cycles. This information is especially useful for determining the circuit reliability, performing dc/ac noise analysis, andchoosingappropriate packagingand cooling techniques for IC's. The power consumption per cl...
Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits
, 2000
"... We present new techniques for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. We investigate four different approaches: (1) timedATPG based approach, (2) probability based approach, (3) genetic algorithm based approach and (4) integer linear programmin ..."
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Cited by 9 (3 self)
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We present new techniques for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. We investigate four different approaches: (1) timedATPG based approach, (2) probability based approach, (3) genetic algorithm based approach and (4) integer linear programming (ILP) approach. The first three approaches produce a tight lower bound on the maximum current. The ILP based approach produces the exact solutions for small circuits, and tight upper bounds of the solutions for large circuits. Our experimental results show that the upper bounds produced by the ILP approach combined with the lower bounds produced by the other three approaches confine the exact solution for the maximum instantaneous current to a small range. Index Terms  Maximum instantaneous current, power supply, timedATPG based, probability based, genetic algorithm based, integer linear programming based. 1. INTRODUCTION Continuous shrinking of the device feature sizes introduces an...
Gatelevel power and current simulation of CMOS integrated circuits
 IEEE TRANSACTIONS ON VLSI SYSTEMS
, 1997
"... In this paper, we present a new gatelevel approach to power and current simulation. We propose a symbolic model of complementary metal–oxide–semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fanin/fanout conditions. Library elements ..."
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Cited by 9 (0 self)
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In this paper, we present a new gatelevel approach to power and current simulation. We propose a symbolic model of complementary metal–oxide–semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fanin/fanout conditions. Library elements are characterized once for all and their models are used during eventdriven logic simulation to provide power information and construct timedomain current waveforms. We provide both global and local patterndependent estimates of power consumption and current peaks (with accuracy of 6 and 10 % from SPICE, respectively), while keeping performance comparable with traditional gatelevel simulation with unit delay. We use VERILOGXL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Webbased user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser.