Results 1 
6 of
6
A Reflective Functional Language for Hardware Design and Theorem Proving
"... This paper introduces reFLect, a functional programming language with reflection features intended for applications in hardware design and verification. The reFLect language is strongly typed and similar to ML, but has quotation and antiquotation constructs. These may be used to construct and decomp ..."
Abstract

Cited by 26 (6 self)
 Add to MetaCart
This paper introduces reFLect, a functional programming language with reflection features intended for applications in hardware design and verification. The reFLect language is strongly typed and similar to ML, but has quotation and antiquotation constructs. These may be used to construct and decompose expressions in the reFLect language itself. The paper motivates and presents the syntax and type system of this language, which brings together a new combination of patternmatching and reflection features targeted specifically at our application domain. It also gives an operational semantics based on a new use of contexts as expression constructors, and it presents a scheme for compiling reFLect programs into the λcalculus using the same context mechanism.
Formal Verification of the VAMP Floating Point Unit
 In CHARME 2001, volume 2144 of LNCS
, 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
Abstract

Cited by 12 (6 self)
 Add to MetaCart
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
Integrating model checking and theorem proving in a reflective functional language
 In IFM
, 2004
"... Abstract. Forte is a formal verification system developed by Intel’s Strategic CAD Labs for applications in hardware design and verification. Forte integrates model checking and theorem proving within a functional programming language, which both serves as an extensible specification language and al ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
Abstract. Forte is a formal verification system developed by Intel’s Strategic CAD Labs for applications in hardware design and verification. Forte integrates model checking and theorem proving within a functional programming language, which both serves as an extensible specification language and allows the system to be scripted and customized. The latest version of this language, called reFLect, has quotation and antiquotation constructs that build and decompose expressions in the language itself. This provides combination of patternmatching and reflection features tailored especially for the Forte approach to verification. This short paper is an abstract of an invited presentation given at the International Conference on Integrated Formal Methods in 2004, in which the philosophy and architecture of the Forte system are described and an account is given of the role of reFLect in the system. 1 The Forte Verification Environment Forte [17] is a formal verification environment that has been very effective on
AssumeGuarantee Validation for STE Properties within an SVA Environment
"... Abstract—Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor execution units. These correctness results are typically obtained under certain ass ..."
Abstract
 Add to MetaCart
Abstract—Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor execution units. These correctness results are typically obtained under certain assumptions about how the verified hardware block’s inputs are driven, as well as assumptions about the values of these inputs. For correct overall operation, the hardware environment within which the verified block resides is expected to satisfy these assumptions. We describe a translation of these proof assumptions into System Verilog Assertions. These are then used as checkers in dynamic validation of the hardware environment within which blocks verified by Symbolic Trajectory Evaluation operate. The result is a pragmatic assumeguarantee method that increases the quality and confidence in verification results, requires little or no modification to the Symbolic Trajectory Evaluation proofs, and leverages preexisting dynamic validation infrastructure. I.
Proof General in Eclipse System and Architecture Overview
"... Interactive theorem proving is the art of constructing electronic proofs. Proof development, based around a proof script, has much in common with program development, based around a program text. Proof developers use rather primitive tools for developing and manipulating proof scripts at present. Th ..."
Abstract
 Add to MetaCart
Interactive theorem proving is the art of constructing electronic proofs. Proof development, based around a proof script, has much in common with program development, based around a program text. Proof developers use rather primitive tools for developing and manipulating proof scripts at present. The Proof General project aims at to change this, by providing powerful generic tools and interfaces. The flagship tool is our Eclipse plugin, which brings the features of a industrialstrength IDE to theorem proving for the first time. In this paper we give an overview of the Eclipse plugin and its underlying architecture. 1. BACKGROUND An electronic proof is the representation of a mathematical proof on machine, usually in a fully formalised way. This means that there is a formal syntax for the logical language, which makes statements of properties to be proven, and for the proof language, which describes how those properties are proved following a set of rules. Electronic proofs are desirable for at least three reasons, when (i) the properties are too complex for human readability, (ii) a high degree of confidence is desired in a proof, or (iii) the proof itself is too detailed to be managed manually. These reasons motivate the typical application areas: • software and hardware verification, dealing with many thousands of correctness conditions [8]; • domain specific logics and metatheory [4]; • deep proofs of mathematical results [6]. With maturing technology, theorem proving inthelarge is becoming more feasible, with significant sized formalisations being attempted in both industry and academia. Recent examples of large efforts include verifying parts of the Pentium
Microprocessor Verification using RTLevel Static Analysis Techniques
"... We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardware designs at the Register Transfer Level (RTL). Antecedent conditioned slicing prunes the verification state space, us ..."
Abstract
 Add to MetaCart
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardware designs at the Register Transfer Level (RTL). Antecedent conditioned slicing prunes the verification state space, using information from the antecedent of a given LTL property. In this work, we model instructions of a pipelined processor into LTL properties, such that the instruction opcode forms the antecedent. We use antecedent conditioned slicing to decompose the problem space of pipelined processor verification on an instruction by instruction basis. We pass the resulting smaller, tractable problems through several lower level verification engines. We thereby verify that every instruction behaves according to the specification and ensure that nontarget registers are not modified by the instruction. We use several Boolean level verification engines that use different algorithms to verify all the instruction classes of a Verilog RTL implementation of the OR1200, an offtheshelf pipelined processor. 1 1.