Abstract not found

1 Introduction Modern architectures have a large gap between thespeeds of the memory and the processor. Several techniques exist to bridge this gap, including mem-ory pipelines (outstanding reads/writes), cache hierarchies, and large register sets. Most of these ar-chitectural features exploit the fact that computations have temporal and/or spatial locality. However,many computations have limited locality, or even no locality at all. In addition, the degree of locality maybe different for different program regions. Such computations may lead to a significant mismatch between

In this paper we present a strategy for run-time profiling to optimize the configuration of a microprocessor dynamically so as to save power with minimum performance penalty. The configuration of the processor changes according to the parallelism in the running program. Experiments on some benchmark programs show good savings in total energy consumption; we have observed a decrease of up to 23% in energy/cycle and up to 8% in energy per instruction. Our proposed approach can be used for energy-aware computing in either portable applications or in desktop environments where power density is becoming a concern. This approach can also be incorporated in larger power management strategies like ACPI.

This paper is meant to be a short introduction to a new paradigm for systems on chip (SoC) design. We refer the interested reader to an extended overview of this problem [1] and to some recent results in this area in industry [21, 10] and academia [4, 5]. The premises are that a component-based design methodology will prevail in the future, to support component re-use in a plug-and-play fashion. At the same time, SoCs will have to provide a functionally-correct, reliable operation of the interacting components. The physical interconnections on chip will be a limiting factor for performance and energy consumption. The international technology roadmap for semiconductors (ITRS) [23] projects that we will be designing multi-billion transistor chips by the end of this decade, with feature sizes around 50nm and clock frequencies around 10GHz. Delays on wires will dominate: global wires spanning a significant fraction of

Many portable systems deploy operating systems (OS) to support versatile functionality and to manage resources, including power. This paper presents a new approach for using OS to reduce the power consumption of IO devices in interactive systems. Low-power OS observes the relationship between hardware devices and processes. The OS kernel estimates the utilization of a device from each process. If a device is not used by any running process, the OS puts it into a low-power state. This paper also explains how scheduling can facilitate power management. When processes are properly scheduled, power reduction can be achieved without degrading performance. We implemented a prototype on Linux to control two devices; experimental results showed nearly 70% power saving on a network card and a hard disk drive.

The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period [5]. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels.

This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: µC/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multi-rate task scheduler reminiscent of typical “roll-your-own” RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz.

This paper presents the design and implementation of a compiler algorithm that effectively reduces the energy usage of memory-bound applications via dynamic voltage scaling (DVS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance penalty. It is implemented as a source-to-source level transformation using the SUIF2 compiler infrastructure. Physical measurements on a laptop with a 600 MHz - 1.2 GHz AMD Athlon 4 processor show that CPU energy savings in the range of 9.17% to 55.65% can be achieved with performance degradation in the range of 0.69% to 6.14% for the SPECfp95 benchmarks. On average, the energy and energy-delay product are reduced by 26.58% and 24.11%, respectively, at the cost of the performance slowdown of 3.26%. This paper also discusses a new methodology which attempts to approximate the minimum energy usage by any DVS algorithm. Our compiler-directed DVS algorithm is within 6% from the "optimal" case. To the best of our knowledge, this is one of the first work that evaluates DVS strategies by physical measurements.

Power and energy consumption has recently become an important issue and consequently, power-aware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system and networking layers. In this survey we concentrate on power-aware design techniques for real-time systems. While the main focus is on hard real-time, soft real-time systems are considered as well. We start with the motivation for focusing on these systems and provide a brief discussion on power and energy objectives. We then follow with a survey of current research on a layer by layer basis. We conclude with illustrative examples and open research challenges. This work provides an overview of poweraware techniques for the real-time system engineer as well as an up-to-date reference list for the researcher.

Dynamic voltage and frequency scaling of the CPU has been identified as one of the most effective ways to reduce energy consumption of a program. This paper discusses a compilation strategy that identifies scaling opportunities without significant overall performance penalty. Simulation results show CPU energy savings of 3.97%-23.75% for the SPECfp95 benchmark suite with a performance penalty of at most 2.53%.