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Synthesis of reactive(1) designs
 In Proc. Verification, Model Checking, and Abstract Interpretation (VMCAI’06
, 2006
"... Abstract. We consider the problem of synthesizing digital designs from their LTL specification. In spite of the theoretical double exponential lower bound for the general case, we show that for many expressive specifications of hardware designs the problem can be solved in time N 3, where N is the s ..."
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Cited by 118 (9 self)
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Abstract. We consider the problem of synthesizing digital designs from their LTL specification. In spite of the theoretical double exponential lower bound for the general case, we show that for many expressive specifications of hardware designs the problem can be solved in time N 3, where N is the size of the state space of the design. We describe the context of the problem, as part of the Prosyd European Project which aims to provide a propertybased development flow for hardware designs. Within this project, synthesis plays an important role, first in order to check whether a given specification is realizable, and then for synthesizing part of the developed system. The class of LTL formulas considered is that of Generalized Reactivity(1) (generalized Streett(1)) formulas, i.e., formulas of the form: ( p1 ∧ · · · ∧ pm) → ( q1 ∧ · · · ∧ qn) where each pi, qi is a boolean combination of atomic propositions. We also consider the more general case in which each pi, qi is an arbitrary past LTL formula over atomic propositions. For this class of formulas, we present an N 3time algorithm which checks whether such a formula is realizable, i.e., there exists a circuit which satisfies the formula under any set of inputs provided by the environment. In the case that the specification is realizable, the algorithm proceeds to construct an automaton which represents one of the possible implementing circuits. The automaton is computed and presented symbolically. 1
Formal verification in hardware design: A survey
, 1997
"... In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing. There are two main aspects to the application of formal methods ..."
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Cited by 110 (0 self)
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In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing. There are two main aspects to the application of formal methods in a design process: The formal framework used to specify desired properties of a design, and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques which have been proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between!regular languages. The verification techniques presented include model checking, automatatheoretic techniques, automated theorem proving, and approaches that integrate the above methods.
METATEM: A Framework for Programming in Temporal Logic
 In REX Workshop on Stepwise Refinement of Distributed Systems: Models, Formalisms, Correctness (LNCS Volume 430
, 1989
"... In this paper we further develop the methodology of temporal logic as an executable imperative language, presented by Moszkowski [Mos86] and Gabbay [Gab87, Gab89] and present a concrete framework, called METATEM for executing (modal and) temporal logics. Our approach is illustrated by the developmen ..."
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Cited by 88 (19 self)
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In this paper we further develop the methodology of temporal logic as an executable imperative language, presented by Moszkowski [Mos86] and Gabbay [Gab87, Gab89] and present a concrete framework, called METATEM for executing (modal and) temporal logics. Our approach is illustrated by the development of an execution mechanism for a propositional temporal logic and for a restricted first order temporal logic.
A Resolution Method for Temporal Logic
 In Proceedings of the Twelfth International Joint Conference on Artificial Intelligence (IJCAI
, 1991
"... In this paper, a resolution method for propositional temporal logic is presented. Temporal formulae, incorporating both pasttime and futuretime temporal operators, are converted to Separated Normal Form (SNF), then both nontemporal and temporal resolution rules are applied. The resolution method ..."
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Cited by 84 (25 self)
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In this paper, a resolution method for propositional temporal logic is presented. Temporal formulae, incorporating both pasttime and futuretime temporal operators, are converted to Separated Normal Form (SNF), then both nontemporal and temporal resolution rules are applied. The resolution method is based on classical resolution, but incorporates a temporal resolution rule that can be implemented efficiently using a graphtheoretic approach. 1 Introduction This report describes a resolution procedure for discrete, linear, propositional temporal logic. This logic incorporates both pasttime and futuretime temporal operators and its models consist of sequences of states, each sequence having finite past and infinite future. A naive application of the classical resolution rule to temporal logics fails as two complementary literals may not represent a contradictory formula, depending on their temporal context. Because of such problems with resolution, the majority of the decision meth...
Temporal Deductive Databases
, 1992
"... We survey a number of approaches to the problem of finite representation of infinite temporal extensions. Two of them, Datalog 1S and Templog, are syntactical extensions of Datalog; the third is based on repetition and arithmetic constraints. We provide precise characterizations of the expressivenes ..."
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Cited by 69 (10 self)
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We survey a number of approaches to the problem of finite representation of infinite temporal extensions. Two of them, Datalog 1S and Templog, are syntactical extensions of Datalog; the third is based on repetition and arithmetic constraints. We provide precise characterizations of the expressiveness and the computational complexity of these languages. We also describe query evaluation methods.
Automating the Addition of FaultTolerance
 Formal Techniques in RealTime and FaultTolerant Systems
, 1926
"... In this paper, we focus on automating the transformation of a given faultintolerant program into a faulttolerant program. We show how such a transformation can be done for three levels of faulttolerance properties, failsafe, nonmasking and masking. For the high atomicity model where the program c ..."
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Cited by 66 (18 self)
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In this paper, we focus on automating the transformation of a given faultintolerant program into a faulttolerant program. We show how such a transformation can be done for three levels of faulttolerance properties, failsafe, nonmasking and masking. For the high atomicity model where the program can read all the variables and write all the variables in one atomic step, we show that all three transformations can be performed in polynomial time in the state space of the faultintolerant program. For the low atomicity model where restrictions are imposed on the ability of programs to read and write variables, we show that all three transformations can be performed in exponential time in the state space of the faultintolerant program. We also show that the the problem of adding masking faulttolerance is NPhard and, hence, exponential complexity is inevitable unless P =NP . 1 Introduction In this paper, we focus on automating the transformation of a faultintolerant program into a fa...
Synthesizing Distributed Systems
, 2001
"... In system synthesis, we transform a specication into a system that is guaranteed to satisfy the speci cation. When the system is distributed, the goal is to construct the system's underlying processes. Results on multiplayer games imply that the synthesis problem for linear specications is un ..."
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Cited by 64 (1 self)
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In system synthesis, we transform a specication into a system that is guaranteed to satisfy the speci cation. When the system is distributed, the goal is to construct the system's underlying processes. Results on multiplayer games imply that the synthesis problem for linear specications is undecidable for general architectures, and is nonelementary decidable for hierarchical architectures, where the processes are linearly ordered and information among them ows in one direction. In this paper we present a signicant extension of this result. We handle both linear and branching specications, and we show that a sucient condition for decidability of the synthesis problem is a linear or cyclic order among the processes, in which information ows in either one or both directions. We also allow the processes to have internal hidden variables, and we consider communications with and without delay. Many practical applications fall into this class. 1 Introduction In system synthesis, we...
Generalized Temporal Verification Diagrams
 IN 15TH CONFERENCE ON THE FOUNDATIONS OF SOFTWARE TECHNOLOGY AND THEORETICAL COMPUTER SCIENCE
, 1994
"... Verification diagrams are a succinct and intuitive way of representing proofs that reactive systems satisfy a given temporal property. We present a generalized verification diagram that allows representation of a proof of any property expressible by a temporal formula. We show that representation of ..."
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Cited by 61 (21 self)
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Verification diagrams are a succinct and intuitive way of representing proofs that reactive systems satisfy a given temporal property. We present a generalized verification diagram that allows representation of a proof of any property expressible by a temporal formula. We show that representation of a proof by generalized verification diagram is sound and complete.
Linear time logic control of discretetime linear systems
 IEEE Transactions on Automatic Control
, 2006
"... Abstract. The control of complex systems poses new challenges that fall beyond the traditional methods of control theory. One of these challenges is given by the need to control, coordinate and synchronize the operation of several interacting submodules within a system. The desired objectives are no ..."
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Cited by 59 (4 self)
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Abstract. The control of complex systems poses new challenges that fall beyond the traditional methods of control theory. One of these challenges is given by the need to control, coordinate and synchronize the operation of several interacting submodules within a system. The desired objectives are no longer captured by usual control specifications such as stabilization or output regulation. Instead, we consider specifications given by Linear Temporal Logic (LTL) formulas. We show that existence of controllers for discretetime controllable linear systems and LTL specifications can be decided and that such controllers can be effectively computed. The closedloop system is of hybrid nature, combining the original continuous dynamics with the automatically synthesized switching logic required to enforce the specification. 1.
Synthesis of faulttolerant concurrent programs
 Proceedings of the 17th ACM Symposium on Principles of Distributed Computing (PODC
, 1998
"... Methods for mechanically synthesizing concurrent programs from temporal logic specifications obviate the need to manually construct a program and compose a proof of its correctness. A serious drawback of extant synthesis methods, however, is that they produce concurrent programs for models of comput ..."
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Cited by 53 (5 self)
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Methods for mechanically synthesizing concurrent programs from temporal logic specifications obviate the need to manually construct a program and compose a proof of its correctness. A serious drawback of extant synthesis methods, however, is that they produce concurrent programs for models of computation that are often unrealistic. In particular, these methods assume completely faultfree operation, i.e., the programs they produce are faultintolerant. In this paper, we show how to mechanically synthesize faulttolerant concurrent programs for various fault classes. We illustrate our method by synthesizing faulttolerant solutions to the mutual exclusion and barrier synchronization problems. Categories and Subject Descriptors: F.3.1 [Logics and Meanings of Programs]: Specifying and Verifying and Reasoning about Programs—logics of programs, mechanical verification, specification