We survey recent research that has appeared in the theoretical computer science literature on algorithmic

Power consumption has been a major concern, both for processor design with high clock rates and embedded systems driven by batteries. Recent support for dynamic frequency and voltage scaling (DVS) in contemporary processor architectures allows software to affect power consumption by varying execution frequency and supply voltage on the fly. However, processors generally enter a sleep state while transitioning between frequencies/voltages. In this paper, we examine the merits of hardware/software co-design for a feedback DVS algorithm and a novel processor capable of executing instructions during frequency/voltage transitions. We study several power-aware feedback schemes based on earliestdeadline-first (EDF) scheduling that adjust the system behavior dynamically for different workload characteristics. An infrastructure for investigating several hard realtime DVS schemes, including our feedback DVS algorithm, is implemented on an IBM PowerPC 405LP embedded board. Architecture and algorithm overhead is assessed for different DVS schemes. Measurements on the experimentation board provide a quantitative assessment of the potential of energy savings for DVS algorithms as opposed to our prior simulation work that could only provide trends. Energy consumption, measured through a data acquisition board, indicates a considerable potential for real-time DVS scheduling algorithms to lower energy up to 64 % over the naïve DVS scheme. Our feedback DVS algorithm saves at least as much and often considerably more energy than previous DVS algorithms with peak savings of an additional 24 % energy reduction. 1.

Abstract — While Dynamic Voltage Scaling (DVS) is an efficient technique in reducing the dynamic energy consumption of a CMOS processor, methods that employ DVS without considering leakage current are quickly becoming less efficient when considering the processor’s overall energy consumption. A leakage conscious DVS voltage schedule may require the processor to run at a higher-than-necessary speed to execute a given set of real-time tasks, which can result in a large number of idle intervals. To effectively reduce the energy consumption during these idle intervals, and therefore the overall energy consumption, the DVS schedule must dictate that the processor both enter and leave the power down state during these idle intervals, while carefully considering the time and energy cost of doing so. In this paper, we present a scheduling technique that can effectively reduce the overall energy consumption for hard real-time systems scheduled according to a fixed priority (FP) scheme. Experimental results demonstrate that a processor using our strategy consumes as less as 15 % of the idle energy of a processor employing the conventional strategy. I.

This paper presents an efficient method to find the optimal intra-task voltage/frequency scheduling for single tasks in practical real-time systems using statistical workload information. Our method is analytic in nature and proved to be optimal. Simulation results verify our theoretical analysis and show significant energy savings over previous methods. In addition, in contrast to the previous techniques in which all available frequencies are used in a schedule, we find that, by carefully selecting a subset of a small number of frequencies, one can still design a reasonably good schedule while avoiding unnecessary transition overheads. 1.

Abstract—Mobile devices primarily processing multimedia data need to support multimedia quality with limited battery energy. To address this challenging problem, researchers have introduced adaptation into multiple system layers, ranging from hardware to applications. Given these adaptive layers, a new challenge is how to coordinate them to fully exploit the adaptation benefits. This paper presents a novel cross-layer adaptation framework, called GRACE-1, that coordinates the adaptation of the CPU hardware, OS scheduling, and multimedia quality based on users ’ preferences. To balance the benefits and overhead of cross-layer adaptation, GRACE-1 takes a hierarchical approach: It globally adapts all three layers to large system changes, such as application entry or exit, and internally adapts individual layers to small changes in the processed multimedia data. We have implemented GRACE-1 on an HP laptop with the adaptive Athlon CPU, Linux-based OS, and video codecs. Our experimental results show that, compared to schemes that adapt only some layers or adapt only to large changes, GRACE-1 reduces the laptop’s energy consumption up to 31.4 percent while providing better or the same video quality. Index Terms—Energy-aware systems, support for adaptation, real-time systems, embedded systems. æ 1

Wearable medical systems, which are used for medical monitoring, assessment, and/or treatment have the essential requirements to be low energy consuming and reliable. They must be energy efficient, so that battery size is minimal, to ensure that the systems are convenient to use. Also, they must be highly reliable, because they are being developed for critical medical applications. In this paper we examine the critical requirement of energy minimization, specifically for wearable medical systems. We present an overview of the general power management schemes, along with more specific approaches tailored to wearable systems. We specifically highlight two medical wearable systems, RFAB and CustoMed, being developed by our group. Finally, we discuss the relationship between reliability and power management, and how this impacts the critical medical systems we are examining. 1.