A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...

A flexible and efficient method for analog circuit partitioning and transistor stacking is presented. The method is based on a novel algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database. An enhanced set of stacks is obtained with respect to placement constraints. Experimental results show the effectiveness of the methods described. 1. Introduction In the last decade, some attempts have been made to develop automation for analog circuit layout design [1, 2, 3, 4]. Since the constraints for analog and digital design are different, the techniques for digital circuits cannot be easily ported to analog design. Analog physical design has to deal with special requirements for matching, symmetry, parasitics and for the variety of transistor sizes. The layout objectives in analog design target layout symmetry and device matching. Typical techniques in analog layout are large device folding, interdigitated structures for symm...

Abstract — This paper deals with the extraction of RC parasitic of SCL inverter submicron layouts. As it is known in VLSI design that the RC parasitic of any design is most crucial and affect all performance of the circuit. SCL is promising logic as it is analog friendly and consumes less power in high speed. For that, Different SCL inverters layouts have been investigated for it is effect on output voltage swing, switching noise and the area. The results show an important affect on the SCL output signals. Post-Simulation was carried out on all proposed layouts using HSPICE and using 0.35u MIMOS Berhad PDK. The layout is done using Virtuous from Cadence whereas the