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A HOL specification of the ARM instruction set architecture
, 2001
"... This report gives details of a hol specification of the arm instruction set architecture. It is shown that the hol proof tool provides a suitable environment in which to model the architecture. The specification is used to execute fragments of arm code generated by an assembler. The specification is ..."
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This report gives details of a hol specification of the arm instruction set architecture. It is shown that the hol proof tool provides a suitable environment in which to model the architecture. The specification is used to execute fragments of arm code generated by an assembler. The specification is based primarily around the third version of the arm architecture, and the intent is to provide a target semantics for future microprocessor verifications. Contents 1
Formalizing Java's Two'sComplement Integral Type in Isabelle/HOL
 In Eighth International Workshop on Formal Methods for Industrial Critical Systems (FMICS’03). ENTCS 80
, 2003
"... We present a formal model of the Java two'scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are p ..."
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We present a formal model of the Java two'scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointed out and clarified. The theory is formally analyzed in Isabelle/HOL, that is, machinechecked proofs for the ring properties and divisor/remainder theorems etc. are provided. This work is suited to build the framework for machinesupported reasoning over arithmetic formulae in the context of Java sourcecode verification.
Verifying ARM6 Multiplication
"... Abstract. The hol4 proof system has been used to formally verify the correctness of the ARM6 microarchitecture. This paper describes the specification and verification of the multiply instructions. The processor’s implementation is based on the modified Booth’s algorithm. Correctness is defined us ..."
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Abstract. The hol4 proof system has been used to formally verify the correctness of the ARM6 microarchitecture. This paper describes the specification and verification of the multiply instructions. The processor’s implementation is based on the modified Booth’s algorithm. Correctness is defined using data and temporal abstraction maps. The ARM6 is a commercial RISC microprocessor that has been used extensively in embedded systems – it has a 3stage pipeline with a multicycled execute stage. This paper describes the approach used in the formal verification and presents some key lemmas. 1
GATE – a general architecture for text engineering
 In Proceedings of the 16th Conference on Computational Linguistics (COLING96). http://citeseer.nj.nec.com/43097.html
, 2004
"... The hol4 proof system has been used to formally verify the correctness of the ARM6 microarchitecture. This paper describes the specification and verification of one instructions class, block data transfers; these are a form of loadstore instruction in which a set of up to sixteen registers can be ..."
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The hol4 proof system has been used to formally verify the correctness of the ARM6 microarchitecture. This paper describes the specification and verification of one instructions class, block data transfers; these are a form of loadstore instruction in which a set of up to sixteen registers can be transferred atomically. The ARM6 is a commercial RISC microprocessor that has been used extensively in embedded systems – it has a 3stage pipeline with a multicycled execute stage. A list based programmer’s model specification of the block data transfers is compared with the ARM6’s implementation which uses a 16bit mask. The models are far removed and reasonably complex, and this poses a verification challenge. This paper describes the approach and some key lemmas used in verifying correctness, which is defined using data and temporal abstraction maps. 1
Managing complexity through abstraction: A refinementbased approach to formalize instruction set architectures
 Newcastle University
, 2011
"... Abstract. Verifying the functional correctness of a processor requires a sound and complete specification of its Instruction Set Architecture (ISA). Current industrial practice is to describe a processor’s ISA informally using natural language often with added semiformal notation to capture the fun ..."
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Abstract. Verifying the functional correctness of a processor requires a sound and complete specification of its Instruction Set Architecture (ISA). Current industrial practice is to describe a processor’s ISA informally using natural language often with added semiformal notation to capture the functional intent of the instructions. This leaves scope for errors and inconsistencies. In this paper we present a method to specify, design and construct sound and complete ISAs by stepwise refinement and formal proof using the formal method EventB. We discuss how the automatically generated Proof Obligations help to ensure selfconsistency of the formal ISA model, and how desirable properties of ISAs can be enforced within this modeling framework. We have developed a generic ISA modeling template in EventB to facilitate reuse. The key value of reusing such a template is increased model integrity. Our method is now being used to formalize the ISA of the XMOS XCore processor with the aim to guarantee that the documentation of the XCore matches the silicon and the silicon matches the architectural intent. 1
18 pages Formalizing Java’s Two’sComplement Integral Type in Isabelle/HOL
"... We present a formal model of the Java two’scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointe ..."
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We present a formal model of the Java two’scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointed out and clarified. The theory is formally analyzed in Isabelle/HOL, that is, machinechecked proofs for the ring properties and divisor/remainder theorems etc. are provided. This work is suited to build the framework for machinesupported reasoning over arithmetic formulae in the context of Java sourcecode verification.
Algebraic Models of Correctness for Abstract Pipelines
"... We apply algebraic tools for modelling microprocessors to the specification, implementation, and verification of an abstract pipelined case study. We employ a model of time based on counting events by means of a clock. We model systems by iterated maps that evolve over time from some initial state. ..."
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We apply algebraic tools for modelling microprocessors to the specification, implementation, and verification of an abstract pipelined case study. We employ a model of time based on counting events by means of a clock. We model systems by iterated maps that evolve over time from some initial state. We define formal correctness conditions, and introduce the onestep theorems that can reduce the complexity of formal verification. The algebraic models provide: (i) modular descriptions of pipelined systems; (ii) equational correctness criteria; and (iii) equational specification and verification techniques for the design of pipelined systems applicable to a range of software systems. 1