This paper gives a survey on cryptographic hash functions. It gives an overview of all types of hash functions and reviews design principals and possible methods of attacks. It also focuses on keyed hash functions and provides the applications, requirements, and constructions of keyed hash functions.

. In this paper we apply the cryptographic finite state machine approach as introduced in [1] to the design of symmetric key block ciphers. Key words in the design approach are simplicity, uniformity, parallelism, distributed nonlinearity and high diffusion. 3-Way is a block cipher with a block and key length of 96 bits. Key components in the construction of 3-Way are a 3-bit nonlinear S-box and a linear mapping that can be described by modular polynomial multiplication in ZZ 12 2 . The arrangement of the components allows software implementations in the range of 10 Mbit/s on a modern PC and dedicated hardware implementations above 1 Gbit/s using standard technology (1:2¯ CMOS). The cipher structure of 3-Way is shown to be surprisingly strong with respect to both linear and differential cryptanalysis. 1 Introduction Essentially a block cipher is a keyed permutive mapping (encryption) together with its inverse (decryption). For a practical block cipher it is important that these two m...

Dedicated hash functions are cryptographically secure compression functions which are designed specifically for hashing. They intend to form a practical alternative for hash functions based on another cryptographic primitive like a block cipher or modular squaring. About a dozen of dedicated hash functions have been proposed in the literature. This paper discusses the design principles on which these hash functions are based.

In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequence generation (Substream) and cryptographic hashing (Subhash). In Substream mode the chip can be used for stream encryption/decryption under control of a 256-bit key. A cryptographic resynchronization mechanism is provided for fast accessibility of encrypted data by legitimate parties. Application fields include the real-time encryption of digital HDTV signals as well as high speed telecommunication and networking such as ATM. The chip has been fabricated within the INVOMEC / EUROCHIP educational VLSI Design Facilities in MIETEC 2:4¯ CMOS technology. Measured samples are operating at encryption / decryption rates of 286 Mbits/sec and hashing rates of 572 Mbits/sec. The operation of the chip is demonstrated by a setup showing the real-time encryption and decryption of digitized PAL color composite video signals...

. ??1? An engineering oriented approach for the design of selfsynchronizing stream ciphers is given. To show that it is useful in practice, an actual design is presented and motivated. This SSSC is claimed to be fast (gate delay 2 XORs), cryptographically secure and easily implementable in hardware (standard cells). Key Words. Self-Synchronizing Stream Ciphers, Cryptographic Hardware, Cryptographic Design. 1 Introduction ??2? Binary self-synchronizing stream ciphers (SSSC) can be distinguished from all other encryption techniques by the ease of synchronization. In spite of their widespread use, these systems have received little attention in the open cryptographic literature. The mostly adopted method to implement a (binary) selfsynchronizing stream cipher is still by using a block cipher (such as DES) in 1-bit CFB mode [2]. Recently Ueli Maurer wrote a paper on the dedicated design of self-synchronizing stream ciphers [7]. Although this paper contains a number of interesting ideas, ...

Abstract. This paper describes and analyzes the security of a general-purpose cryptographic function design, with application in RFID tags and sensor networks. Based on these analyzes, we suggest minimum parameter values for the main components of this cryptographic function, called ARMADILLO. With fully serial architecture we obtain that 2923 GE could perform one compression function computation within 176 clock cycles, consuming 44 µW at 1 MHz clock frequency. This could either authenticate a peer or hash 48 bits, or encrypt 128 bits on RFID tags. A better tradeoff would use 4030 GE, 77 µW of power and 44 cycles for the same, to hash (resp. encrypt) at a rate of 1.1 Mbps (resp. 2.9 Mbps). As other tradeoffs are proposed, we show that ARMADILLO offers competitive performances for hashing relative to a fair Figure Of Merit (FOM). 1

1.4 Simple XOR