Variation is a key concern in semiconductor manufacturing and is manifest in several forms. Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies. Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation. Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed. In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer--die interaction contributions to spatial variation. Waferlevel estimation methods include filtering, spline, and regression based approaches. Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods; important issues include spectral interpolation and sampling requirements. Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation; spline- and frequency-based methods are proposed for this modeling. Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits.

Introduction: Sources of Variation Variation is the deviation from intended or designed values for a structure or circuit parameter of concern. The electrical performance of microprocessors or other integrated circuits are impacted bytwo sources of variation. First, environmental factors are those which arise during the operation of a circuit, and include variations in power supply, switching activity, and temperature of the chip or across the chip. These variations depend primarily on architectural and operating decisions such as power grid design and component placement. Time-varying (temporal) variation in these environment parameters can be a significant design concern. Circuit robustness to noise, cross-talk, and time- and switching-related aging or reliability factors must be considered carefully during circuit design. In this chapter, we will focus on a second category of variation sources. Physical factors during manufacture result in struct

We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed methods were successfully applied to two example circuits for an industrial fabrication process.

Abstract—In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as and hƒƒ, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network. Index Terms—Clock skew, manufacturability, mismatch, process variations, statistical design, timing analysis.

This paper presents a discussion on several methods that can be used to improve the testability of mixed-signal integrated circuits. We begin by outlining the role of test, and its impact on product cost and quality. A brief look at the pending test crises for mixedsignal circuits is also considered. Subsequently, we shall outline several common test strategies, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. The remainder of the paper will describe several analog test buses and circuits for built-in self-test applications. 1.

This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.

Composite microsystems that integrate mechanical and fluidic components with electronics are emerging as the next generation of system-on-a-chip. Custom microsystems are expensive, inflexible, and unsuitable for high-volume production. The authors address this problem by leveraging hardware/software codesign principles to design reconfigurable composite microsystems. They partition the system design parameters into nonreconfigurable and reconfigurable categories. In this way, operational flexibility is enhanced and the microsystems are designed for a wider range of application. In addition, the Taguchi robust design method is used to make the system robust, and response surface methodologies are used to explore the widest performance range for the system. A case study is presented for a microvalve, which serves as a representative microelectrofluidic device.

In this paper, a new method for analog circuit sizing with respect to manufacturing and operating tolerances is presented. Two types of robustness objectives are presented, i.e. parameter distances for the nominal design and worstcase distances for the design centering. Moreover, the generalized boundary curve is presented as a method to determine a parameter correction within an iterative trust region algorithm. Results show that a significant reduction in computational costs is achieved using the presented robustness objectives and generalized boundary curve.

In this report a method for the design centering of analog circuits, based on worstcase distances (WCD) is presented. In order to keep the linearization error small, only the WCDs and not the strongly nonlinear objective function itself is linearized. For the resulting nonlinear trust-region problem the generalized boundary curve (GBC) is derived as a method to determine a solution with a good ratio between error reduction and norm of the parameter correction. This parameter correction is used in a standard iterative trust-region optimization algorithm. Results calculated on a circuit example show a signifcant reduction of iterations compared to a standard gradient-based optimization algorithm. Thus, design centering becomes applicable within industrial analog circuit design.

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based on SPICE simulation data with device-level accuracy. We will prove that this problem corresponds to solving a non--convex optimization problem without local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time--consuming nature of hand--crafted analytic model generation. Experimental results illustrate the capabilities and effectiveness of the presented modeling technique.