We present a novel technique that combines logic resynthesis and linear placement in order to alleviate routing congestion in bit-sliced layout. In this approach, we restructure the logic using an intermediate placement solution and then adjust the placement to match the new logic structure. This ability to change logic structure during layout allows us to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been re-synthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared to the original designs. 1 Introduction One of the critical problems encountered in the design of today's VLSI circuits is optimization of the interconnect. This is because with submicron MOS technology and increased density and performance requirements on designs, interconnects have become a major factor in determining t...

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...

We present a general multi-layer area router for performing detailed routing in integrated circuits. This router is based on a novel grid construction scheme which considers the differing design rules of the routing layers and produces more wiring tracks than a uniform grid scheme. Our router is very general and flexible and is designed to handle all the physical constraints of a CMOS custom cell layout problem for an arbitrary number of routing layers. The router has been incorporated into the Custom Cell Synthesizer project at MCC. It has produced better results than uniform gridded routers and improved the capability of the system by providing routing flexibility and supporting features needed to handle a wide range of design styles in generating CMOS custom cells. 1 Introduction Automatic custom cell synthesis presents some unique constraints to the routing problem not present in simple channel routing [1], [2] and switchbox routing models [3], [4]. The boundary of the routing pr...

this paper formalises the way in which a schematic of a static CMOS gate is converted into an optimised mask layout. The basic design steps consists of: