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14
Automatic Generation of Functional Vectors Using The Extended Finite State Machine Model
 ACM Trans. on design Automation of Electronic Systems
, 1996
"... We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing or power estimation. A highlevel description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms th ..."
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Cited by 45 (1 self)
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We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing or power estimation. A highlevel description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms the highlevel description, in VHDL or C, of a circuit into an extended finite state machine (EFSM) model that is used to generate functional vectors. The EFSM model is a generalization of the traditional state machine model. It is a compact representation of models with local data variables and preserves many nice properties of a traditional state machine model. The theoretical background of the EFSM model will be addressed in this paper. Our method guarantees that the generated vectors cover every statement in the highlevel description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flipflops can be ge...
Explorations of Sequential ATPG Using Boolean Satisfiability
 In 11th VLSI Test Symposium
, 1993
"... This paper presents a sequential test generation method based on Boolean satisfiability. The method produces nearminimal test sizes. We discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS89 benchmark circuits an ..."
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Cited by 18 (0 self)
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This paper presents a sequential test generation method based on Boolean satisfiability. The method produces nearminimal test sizes. We discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS89 benchmark circuits and comparisons with previously published results are presented. 1 Introduction In this paper we present a sequential test generation method based on Boolean satisfiability [9]. The purpose is to demonstrate the feasibility of Boolean satisfiability in sequential test generation, and to produce nearminimal number of test vectors in order to show how much bigger test sizes are being produced by more mature test generation systems, such as VERITAS [5], STEED [8], and STALLION [10]. The nearminimal test size is obtained by using a forward time processing (FTP) technique similar to the S Algorithm by Breuer [2]. Even though a combination of reverse time processing and forward time processing te...
On Verifying the Correctness of Retimed Circuits
 Great Lakes Symposium on VLSI
, 1996
"... We address the problem of verifying a retimed circuit. After retiming, some latches in a sequential circuit are repositioned to reduce the clock cycle time and thus the behavior of the combinational portion is changed. Here, we present a novel approach to check the correctness of a retimed circuit a ..."
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Cited by 15 (2 self)
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We address the problem of verifying a retimed circuit. After retiming, some latches in a sequential circuit are repositioned to reduce the clock cycle time and thus the behavior of the combinational portion is changed. Here, we present a novel approach to check the correctness of a retimed circuit according to the definition of 3valued equivalence. This approach is based on our verification framework using sequential ATPG techniques. We further incorporate an algorithm to preprocess the circuits and make the verification process even more efficient. For the first time, we will present the experimental results of verifying the retimed circuits with hundreds of flipflops on ISCAS89 benchmark circuits. 1 Introduction Retiming has been proposed as a technique to optimize a sequential circuit for quite some time [7]. This technique explores the freedom of repositioning the latches to reduce the clock cycle time or to minimize the number of latches. [8,9,13,14]. Since retiming can be p...
Time Efficient Automatic Test Pattern Generation Systems
, 1994
"... Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinati ..."
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Cited by 11 (0 self)
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Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinational and sequential circuits. First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits. This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT). At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses. Further, for concurrent engineering design environments, an incremental ATPG concept is introduced. When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to...
FsmTest: Functional Test Generation for Sequential Circuits
 INTEGRATION: the VLSI Journal
, 1996
"... This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating seque ..."
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Cited by 8 (4 self)
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This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating sequence, referred to as EUIO is proposed. Overlapping is accomplished to reduce the test length. In most cases, test length and CPU time requirements are substantially lower compared with gatelevel ATPGs. Techniques are also introduced to preserve a high fault coverage. Evaluation on MCNC benchmarks has shown the effectiveness of the test algorithm both at functional and gate levels, while achieving in most cases 100% coverage of single stuckat faults. I. Introduction The problem of testing sequential architectures has been widely treated at gate level (e.g. [Ben84] [M&A88] [C&C89] [ACA89] [K&J89] [N&P90] [GDN91]), but the computational requirements are in most cases unmanageable for large ci...
Deterministic Test Pattern Generation Techniques for Sequential Circuits
 in Proc. of the VLSI Test Symp
, 2000
"... This paper presents new test generation techniques for improving the averagecase performance of the iterative logic array based deterministic sequential circuit test generation algorithms. To be able to assess the effectiveness of the proposed techniques, we have developed a new ATPG system for seq ..."
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Cited by 4 (1 self)
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This paper presents new test generation techniques for improving the averagecase performance of the iterative logic array based deterministic sequential circuit test generation algorithms. To be able to assess the effectiveness of the proposed techniques, we have developed a new ATPG system for sequential circuits, called ATOMS, and we have incorporated these techniques into the test generator. ATOMS achieved very high fault coverages in a short amount of time for the ISCAS89 sequential benchmark circuits, demonstrating the effectiveness of these techniques on the test generation performance. 1 Introduction Although scan based design for testability techniques can convert a sequential circuit into a combinational circuit for testing purposes, in some cases, the cost of full scan can be prohibitive in both area overhead and performance degradation. Therefore, efficient sequential circuit test generation algorithms are very important for producing high quality VLSI circuits. The prob...
Functional test generation for synchronous sequential circuits
 IEEE Trans. on CAD/ICAS
, 1996
"... AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these test ..."
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Cited by 2 (0 self)
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AbstractWe present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cubebased test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of timeframes and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gatelevel stuck faults that is higher than a gatelevel sequentialcircuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementationindependent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.
Sequential Test Generators: Past, Present and Future
 INTEGRATION, the VLSI journal
, 1998
"... With the growth in complexity of VLSI circuits, test generation for sequential circuits is becoming increasingly difficult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits ..."
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Cited by 2 (0 self)
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With the growth in complexity of VLSI circuits, test generation for sequential circuits is becoming increasingly difficult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more effective and powerful sequential test generators. In this paper we describe and illustrate the working of existing sequential circuit test generation algorithms for the VLSI circuits. We also categorize all sequential testing algorithms, and summarize their relative advantages and disadvantages.
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
 Proc. Design Automation Conf
, 1994
"... A low overhead DFT technique, called clockgrouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault coverage for circuits by exercising greater control over flipflop clocks in the test mode. In the test mode, the flipflop ..."
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Cited by 1 (0 self)
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A low overhead DFT technique, called clockgrouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault coverage for circuits by exercising greater control over flipflop clocks in the test mode. In the test mode, the flipflops are partitioned into different clockgroups. The flipflops in each clock group can be either clocked or not clocked, independent of the flipflops in the other groups. This flexibility is used to enhance the number of different (v 1 ; v 2 ) test pairs that can be applied to the state inputs of the circuit thereby increasing coverage of delay faults. Experimental data on benchmark circuits shows that high fault coverage can be obtained by using only two clock groups in most circuits. The proposed clock grouping methodology can be applied to nonscan circuits as well. In fact, it can provide a DFT solution for high speed data path circuits where the performance penalties of conventional DFT...
A Complete Testing Strategy Based on Interacting and Hierarchical FSMs
"... Controldominated devices are usually modeled as a composition of finite state machines. FSMs can be hierarchically composed to dominate the modeling complexity or can be aggregated into an interacting architecture to partition a complex behavior. A hierarchical or interacting FSMs based representat ..."
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Controldominated devices are usually modeled as a composition of finite state machines. FSMs can be hierarchically composed to dominate the modeling complexity or can be aggregated into an interacting architecture to partition a complex behavior. A hierarchical or interacting FSMs based representation can be extracted from a device's description given by means of a hardware description language. The core of the paper concerns the definition of a complete testing strategy based on the comparison between these FSMs representations and the structural representations of the device. This comparison simplifies the testing problem by using the functional information to perform scan insertion, redundancies removal and test pattern generation considering the actual stuckat fault model on the gatelevel implementation. Therefore, a fully testable implementation can be thus obtained even for such devices which cannot be satisfactorily analyzed at the gate level. 1 Introduction The problem of ...