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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
Embedding Hardware Verification within a Commercial Design Framework
 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME 93), Lecture Notes in Computer Science
, 1993
"... . A methodology for verifying complex circuits is presented, based on a strong coupling of design verification with the hierarchical design process. This goal has been achieved by integrating MEPHISTO, a tool for semiautomated hardware verification, into a commercial design framework. MEPHISTO dec ..."
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. A methodology for verifying complex circuits is presented, based on a strong coupling of design verification with the hierarchical design process. This goal has been achieved by integrating MEPHISTO, a tool for semiautomated hardware verification, into a commercial design framework. MEPHISTO decomposes the verification goal by a set of hardwarespecific proof tactics and provides strategies for synthesizing preverified regular components. In case of erroneous implementations, MEPHISTO aids the designer in debugging the circuit by generating a counter model, i.e. input stimuli where specification and implementation behave differently. 1 Introduction To guarantee reliable circuits especially in safety critical applications, and to avoid time consuming and costly redesigns, tools for checking design errors in circuits are mandatory. Usually, this is accomplished by specifying the desired functions and properties of the chip and proving formally that a given implementation behaves a...
The FAUST  Prover
, 1992
"... Introduction Unfortunately firstorder logic has certain limitations which are felt in many applications such as in hardware verification. The use of proof assistants like the HOL system ([Gord88]) is therefore resorted to. However many theorems of higher order logic can also be proven by methods o ..."
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Introduction Unfortunately firstorder logic has certain limitations which are felt in many applications such as in hardware verification. The use of proof assistants like the HOL system ([Gord88]) is therefore resorted to. However many theorems of higher order logic can also be proven by methods of first order logic as well. Being aware of this situation, we have implemented a prover based on Sequent Calculus within the HOL system, which can be used to mechanize proofs of necessary, but tedious lemmata required for a large proof in HOL. In order to find an efficient implementation, we have introduced the concept of unification in our prover. These modifications have resulted in a calculus called the "restricted sequent calculus "(RSEQ) and an automatic prover based on it called FAUST 1 2 . The well known sequent calculus 3 (SEQ) introduced by Gentzen [Gent35] has a major disadvantage as far as the so called<F25.