In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor et al. [20] and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement. The density is controlled by white-space re-allocation using partitioning and cut-line shifting during global placement and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the global placement and macro shifting to find better macro positions. Experimental results show that our placer obtains the best published results. 1.

this article, we use the word "scalability" in the practical, operational sense and therefore consider not just ) algorithms but rather any framework likely to have applicability lasting for several technology generations and circuit-size ranges

Abstract—Recursive bisection is a popular approach for large scale circuit placement problems, combining a high degree of scalability with good results. In this paper, we present a bisection-based approach for both standard cell and mixed block placement; in contrast to prior work, our horizontal cut lines are not restricted to row boundaries. This technique, which we refer to as a fractional cut, simplifies mixed block placement and also avoids a narrow region problem encountered in standard cell placement. Our implementation of these techniques in the placement tool Feng Shui 2.6 retains the speed and simplicity for which bisection is known, while making it competitive with leading methods on standard cell designs. On mixed block placement problems, we obtain substantial improvements over recently published work. Half perimeter wire lengths are reduced by 29 % on average, compared to a flow based on Capo and Parquet; compared to mPG-ms, wire lengths are reduced by 26 % on average. Index Terms—Circuit placement, design automation, mixed size placement, placement legalization, recursive bisection. I.

Abstract — In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all previous placement approaches optimize some very primitive interconnect models during placement. These models are far from the actual interconnect implementation in the routing stage. As a result, placement solution considered to be good by primitive interconnect models may turn out to be poor after routing. In addition, the placement may not even be routable and timing closure may not be achievable. In this paper, we propose to address the inconsistency between the placement and routing objectives by fully integrating global routing into placement. As a first attempt to this novel approach, we focus on routability issue. We call the proposed algorithm for routing congestion minimization IPR (Integrated Placement and Routing). To ensure the algorithm to be computationally efficient, efficient placement and routing algorithms FastPlace, FastDP and FastRoute are integrated, and well-designed methods are proposed to integrate them efficiently and effectively. Experimental results show that IPR reduces overflow by 36%, global routing wirelength by 3.6%, and runtime by 36% comparing to ROOSTER [5], which is the previous best academic routabilitydriven placer.

Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental changes to the layout and netlist due to physical synthesis techniques without perturbing the original metrics. We present an incremental placement approach using floorplan sizing to manage the resources and demands of the whole chip region in order to accommodate the changes due to gate sizing and buffer insertion. The experimental results show that this approach can accommodate a wide range of incremental changes without a loss in wirelength and routability. Most important, it also maintains the stability of a placement such that the convergence of physical synthesis iterations can be greatly enhanced. 1.

In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor et al. and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results.

Abstract—This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifies congested regions of the chip and incorporates the model of the routed wirelength into the objective function in order to effectively alleviate these regions from congestion. The method is integrated in the analytical placement framework and the two-level structure improves the scalability of the placer and speeds up the algorithm. The proposed analytical placer provides the best-so-far average routed wirelength in the IBM version2 benchmark suite. I.

Inspired by recent success of analytical placers that use a logarithmsum-exponential (LSE) to smooth half-perimeter wirelength (HPWL), we consider in this paper two alternative smoothing methods for HPWL by recursive extension of two-variable max functions. A limited memory Quasi-Newton solver is applied to solve the objective function combining both the smoothing function of HPWL and the penalty function that arises from cell density constraints. Experimental results show that our flow using these two smoothing functions and the solver produces placements with comparable HPWL compared to LSE smoothing-based methods. Our placement flow also produces placements with comparable routability and routed wirelength but with shorter runtime. 1.

Abstract — In this paper, we describe a new via-configurable routing architecture which shows much better throughput and performance than the previous structures. We demonstrate how to construct a single-viamask fabric to reduce further the mask cost, and we analyze the penalties which it incurs. To solve the routability problem commonly existing in fabric-based designs, an efficient white-space allocation scheme is suggested, which provides a fast design convergence and early prediction of the circuit mappability to a given fabric. I.

Dramatic progress has been made in algorithms for placement and routing over the last 5 years, with improvements in both speed and quality. Combining placement and routing into a joint optimization has also been proposed. However, it remains unclear if the benefits would be significant enough to justify major changes in commercial tools. CRISP addresses this challenge and is the first tool to demonstrate tangible benefits of combined place-and-route optimization including fewer global routing detours, reduced detailed routing violations and runtime, and even shrinking the floorplan of a commercial design. We employ fast global routing to choose standard cells to temporarily inflate and iteratively spread for congestion reduction. Spreading only in congested regions, we enable die area reduction by facilitating routing with high area utilization. 1.