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A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time. Experiments on standard GSRC industry benchmarks compare an implementation, called PATOMA, to the Traffic floorplanner and to both the default and high-effort modes of the Parquet-2 floorplanner. With all blocks hard, PATOMA’s average wirelength is 38 % shorter than Traffic’s in the same run time. With all blocks soft, PATOMA on average produces wirelengths 16 % shorter than Parquet-2’s default mode and runs 37 ¢ faster. Compared to the high-effort mode of Parquet-2, PATOMA’s average wirelength is 8 % shorter, and it runs 824 ¢ faster, on average. I.

We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored the adaptability of APlace to multiple contexts with good quality of results. For example, the framework was extended to traditional wirelength-driven standard-cell placement in [3, 5], achieving good results in placed HPWL and routed final wirelength. The framework was also extended to top-down multilevel placement, congestion-directed placement, mixed-size placement, timing-driven placement, I/O-core co-placement and constraint handling for mixed-signal contexts [3, 4, 5]. In this work, we have modified the implementation of APlace for speed and scalability. Improvements have been made in clustering, legalization and detailed placement strategies, as well as via a distributable solution framework for both global and detailed placement phases.

A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented.

Abstract — In this paper, we present FastPlace 2.0 – an efficient, flat analytical placer to handle the mixed-mode placement problem. The main contributions of our work are: (1) Extensions to the global placement framework of FastPlace [1] to handle mixed-mode designs. (2) An efficient and optimal minimum perturbation macro legalization algorithm applied after global placement to resolve overlaps among the macros. (3) An efficient legalization scheme to legalize the standard cells among the segments created after fixing the movable macros. (4) An efficient and effective detailed placement algorithm to further minimize the half-perimeter wirelength. On the ISPD 02 Mixed-Size placement benchmarks [2], our placer is ¨ and faster than state-of-the-art academic

... based on infrastructure developed independently by individual contributors. This has led to fragmentation in the community, where interaction, data interchange and comparison of results between tools are difficult. We discuss our early experience with the OpenAccess Gear system, an open source software initiative intended to provide pieces of the critical integration and analysis infrastructure that are taken for granted in proprietary tools, but often wholly absent in research tools. Built on top of the widely available OpenAccess database, OA Gear provides components such as industrial-strength static timing analysis and extensible layout and netlist visualization. We discuss preliminary results from two on-going research efforts that have adopted OA Gear as their infrastructure: retrofitting the University of Michigan Capo placer into this environment, and the addition of a timing-driven capability to the Carnegie Mellon Warp placer.

This chapter is focused on the physical design for system-on-a-chip (SOC). Physical design refers to all synthesis

Abstract—In this paper, we propose the first metal-densitydriven (MDD) placement algorithm to reduce chemical– mechanical planarization/polishing (CMP) variation and achieve higher routability. To efficiently estimate metal density and thickness, we first apply a probabilistic routing model and then a predictive CMP model to obtain the metal-density map. Based on the metal-density map, we use an analytical placement framework to spread blocks to reduce metal-density variation. Experimental results based on BoxRouter and NTUgr show that our method can effectively reduce the CMP variation. By using our MDD placement, for example, the topography variation can be reduced by up to 38 % (23%) and the number of dummy fills can be reduced by up to 14 % (8%), compared with those using wirelength-driven (cell-density-driven) placement. The results of our MDD placement can also lead to better routability. Index Terms—Manufacturability, physical design, placement, VLSI.

c○Chaomin Luo 2008I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. The floorplanning problem aims to arrange a set of rectangular modules on a rectangular chip area so as to optimize an appropriate measure of performance. This problem is known to be NP-hard, and is particularly challenging if the chip dimensions are fixed. Fixed-outline floorplanning is becoming increasingly important as a tool to design flows in the hierarchical design of Application Specific Integrated Circuits and System-On-Chip. Therefore, it has recently received much attention. A two-stage convex optimization methodology is proposed to solve the fixedoutline floorplanning problem. It is a global optimization problem for wirelength minimization. In the first stage, an attractor-repeller convex optimization model provides the relative positions of the modules on the floorplan. The second stage places and sizes the modules using convex optimization. Given the relative positions of the

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