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Reduced Power Dissipation Through Truncated Multiplication
 in IEEE Alessandro Volta Memorial Workshop on Low Power Design
, 1999
"... Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi ..."
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Cited by 19 (5 self)
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Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. 1: Introduction Highspeed parallel multipliers are fundamental building blocks in digital signal processing systems [1]. In...
Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks
, 2005
"... The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization an ..."
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Cited by 2 (0 self)
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The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of four parallel digital multipliers implemented using low power 10 transistor (10T) adders and conventional CMOS adder cells. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. Multipliers realized using the Static Energy Recovery Full adder (SERF) circuit consumed considerably less power compared to 10T and static CMOS based multipliers for all the configurations studied. Furthermore, the difference between the power consumption of the 10 transistor based multipliers and 28T multipliers is significant at 180 nm, but not at 70 nm. For smaller geometry sizes down to 70 nm, the propagation delay of the multipliers implemented with 10 transistors translates to a better performance measure. CarrySave Multipliers had better PDP range than the other multipliers for all the three adder submodule designs. The
Reconfigurable Decimation Filter
"... Decimation filter is used to reduce the sampling rate for succeeding stages of an oversampling ADC. The speed of a successiveapproximation ADC predominately depends on the decimator speed. This necessitates a need to design a high speed decimation filter to improve the overall system performance. A ..."
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Decimation filter is used to reduce the sampling rate for succeeding stages of an oversampling ADC. The speed of a successiveapproximation ADC predominately depends on the decimator speed. This necessitates a need to design a high speed decimation filter to improve the overall system performance. A reconfigurable architecture is applied for the design of decimator to serve this purpose. Results show that delay of a Reconfigurable Decimator is reduced by 29.74 % compared to a
Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture
"... Fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and speed of the DSPs is mainly determined by the speed of its multipliers. Multiplication is the most fundamental operation with intensive arithmetic computations. Two important parameters associated with multi ..."
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Fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and speed of the DSPs is mainly determined by the speed of its multipliers. Multiplication is the most fundamental operation with intensive arithmetic computations. Two important parameters associated with multiplication algorithms performed in DSP applications are latency and throughput. Latency is the “real delay of computing a function”. Throughput is a measure of “how many computations can be performed in a given period of time”. The execution time of most DSP algorithms is dependent on its multipliers, and hence need for high speed multiplier arises. Urdhva tiryakbhyam sutra performs faster for small inputs and Nikhilam sutra for larger inputs. Here a novel Integrated Vedic multiplier architecture, which by itself selects the appropriate multiplication sutra based on the inputs, is proposed. So depending on inputs, whichever sutra is faster, that sutra is selected by the proposed integrated Vedic multiplier architecture. In the simulation results, it can be seen that Urdhva performs faster for small inputs, but Nikhilam performs better for large inputs (more than twice as much for 64 bit multiplicands).