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Reduced Power Dissipation Through Truncated Multiplication
 in IEEE Alessandro Volta Memorial Workshop on Low Power Design
, 1999
"... Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi ..."
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Cited by 26 (7 self)
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Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. 1: Introduction Highspeed parallel multipliers are fundamental building blocks in digital signal processing systems [1]. In...
Transitionactivity aware design of reductionstages for parallel multipliers
 in Proc. of Great Lakes Symposium on VLSI
, 2007
"... We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least signi ..."
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Cited by 2 (2 self)
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We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least significant bits. The same is the case for individual signals within the multiplier. Our interconnect reorganization exploits this to reduce the overall switching activity, thus reducing the multiplier’s power consumption. We have developed a CAD tool that reorganizes the connections within the multiplier architecture in an optimized way. Since the applied heuristic requires power estimation, we have also developed a very fast estimator fine tuned for parallel multipliers. The CAD tool automatically generates gatelevel VHDL code for the optimized multipliers. This code and code for unoptimized multipliers have been compared using state of the art power estimation tools. The reduction in power consumption ranges from 7 % up to 23 % and can be achieved without any noticeable overhead in performance and area.
Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks
, 2005
"... The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization an ..."
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Cited by 2 (0 self)
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The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of four parallel digital multipliers implemented using low power 10 transistor (10T) adders and conventional CMOS adder cells. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. Multipliers realized using the Static Energy Recovery Full adder (SERF) circuit consumed considerably less power compared to 10T and static CMOS based multipliers for all the configurations studied. Furthermore, the difference between the power consumption of the 10 transistor based multipliers and 28T multipliers is significant at 180 nm, but not at 70 nm. For smaller geometry sizes down to 70 nm, the propagation delay of the multipliers implemented with 10 transistors translates to a better performance measure. CarrySave Multipliers had better PDP range than the other multipliers for all the three adder submodule designs. The
A lowerror and areatime efficient fixedwidth Booth’s multiplier
 IEEE Int. Midwest Symp. Circuits Syst
, 2003
"... In this paper, we develop a new methodology for designing a lowererror and areatime efficient 2 scomplement fixedwidth Booth multiplier that receives two nbit numbers and produces an nbit product. By properly choosing the generalized index and binary thresholding, we derive a better errorcojm ..."
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In this paper, we develop a new methodology for designing a lowererror and areatime efficient 2 scomplement fixedwidth Booth multiplier that receives two nbit numbers and produces an nbit product. By properly choosing the generalized index and binary thresholding, we derive a better errorcojmpensation bias to reduce the truncation error. Since the proposed errorcompensation bias is realizable, the constructing lowerror fixedwidth Booth multiplier is areatime efficient for VLSI implementation. Finally, we successfully apply the proposed fixedwidth Booth multiplier to speech signal processing. The simulation results show that the perfoirnance isi stiperior to that using the directtruncation fixedwidth Booth multiplier. 1.
Power Optimized Partial Product Reduction Interconnect Ordering in Parallel Multipliers
"... Abstract — When designing the reduction tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The transition activities vary significantly for different internal partial products. In this work we propose a method for generation of ..."
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Abstract — When designing the reduction tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The transition activities vary significantly for different internal partial products. In this work we propose a method for generation of powerefficient parallel multipliers in such a way that its partial products are connected to minimize activity. The reduction tree is designed progressively. A Simulated Annealing optimizer uses power cost numbers from a specially implemented probabilistic gatelevel power estimator and selects a powerefficient solution for each stage of the reduction tree. VHDL simulation using ModelSim shows a significant reduction in the overall number of transitions. This reduction ranges from 15 % up to 32 % compared to randomly generated reduction trees and is achieved without any noticeable area or performance overhead. I.
International Journal of Electronics and Computer Science Engineering 615 Available Online at www.ijecse.org ISSN 22771956 Design of LowError FixedWidth Modified Booth Multiplier
"... Abstract The fixedwidth multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This paper presents the design of lowerror fixedwidth modified Booth multiplier. To reduce the ..."
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Abstract The fixedwidth multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This paper presents the design of lowerror fixedwidth modified Booth multiplier. To reduce the truncation error, we first slightly modify the partial product matrix of Booth multiplication and then derive an effective error compensation function that makes the error distribution be more symmetric to and centralized in the error equal to zero, leading the fixedwidth modified Booth multiplier to very small mean and meansquare errors. In addition, a simple compensation circuit mainly composed of the simplified sorting network is also proposed. The Carry Prediction method is based on a logical computation followed by a simplification process. Compared to the previous circuits, the proposed error compensation circuit can achieve a tiny mean error and a significant reduction in meansquare error while maintaining the approximate hardware overhead.
Int. J. Advanced Networking and Applications Volume: 03, Issue: 01, Pages:10311034 (2011)
, 1031
"... ABSTRACTThis paper presents C 2 Mos register Pipelined Modified Booth Multiplier (PMBM) to improve the speed of the multiplier by allowing the data parallel. The pipeli ..."
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ABSTRACTThis paper presents C 2 Mos register Pipelined Modified Booth Multiplier (PMBM) to improve the speed of the multiplier by allowing the data parallel. The pipeline registers are designed with two pmos and two nmos transistors in series which is C 2 Mos. Wallace multiplier also used to improve the speed of the multiplier with Carry Save Addition. 16Transitor Full adders are used for better performance of the multiplier. The PMBM is 28.51 % more speed than the Modified Booth Multiplier (MBM). This is calculated with TSMC 0.18um technology using Hspice.
Design of a low power and high performance digital multiplier
"... Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices.The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processor ..."
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Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices.The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency.Multiplier is the most commonly used circuit in the digital devices. Multiplication is one of the basic functions used in digital signal processing. Full Adder is the main block of power dissipation in multiplier. So reducing the power dissipation of full adder ultimately reduces the power dissipation of multiplier. In this paper a XNOR gate using three transistors has been presented. A single bit full adder using eight transistors has been designed using XNOR cell, which shows power dissipation of 620.5μ W. A 4x4 Wallace tree multiplier has been implemented by using the proposed 8T adder. Simulations have been carried out by using cadence tool based on gpdk180nm CMOS technology KeywordsCMOS, exclusiveOR (XOR), exclusiveNOR (XNOR), full adder, low power, multiplier. I.
A FRAMEWORK FOR THE DESIGN OF ERRORAWARE POWER EFFICIENT FIXEDWIDTH BOOTH MULTIPLIERS
"... In this paper, a framework of designing a lowerror and powerefficient two’scomplement fixedwidth Booth multiplier that receives two nbit numbers and produces an nbit product is proposed. The design methodology of the framework involving four steps results in one better errorcompensation bias. ..."
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In this paper, a framework of designing a lowerror and powerefficient two’scomplement fixedwidth Booth multiplier that receives two nbit numbers and produces an nbit product is proposed. The design methodology of the framework involving four steps results in one better errorcompensation bias. The better errorcompensation bias can be mapped to a simple lowerror fixedwidth Booth multiplier with a little penalty of power consumption. For the benchmark of 8x8 multipliers, the simulation results show that a reduction of 82.04 % average error compared to that using the directtruncated fixedwidth Booth multiplier can be obtained. Moreover, the power consumption can be saved 40.68 % compared to that of fullprecision Booth multiplier design. 1.
Algorithms, Design
"... We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least sig ..."
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We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least significant bits. The same is the case for individual signals within the multiplier. Our interconnect reorganization exploits this to reduce the overall switching activity, thus reducing the multiplier’s power consumption. We have developed a CAD tool that reorganizes the connections within the multiplier architecture in an optimized way. Since the applied heuristic requires power estimation, we have also developed a very fast estimator fine tuned for parallel multipliers. The CAD tool automatically generates gatelevel VHDL code for the optimized multipliers. This code and code for unoptimized multipliers have been compared using state of the art power estimation tools. The reduction in power consumption ranges from 7 % up to 23 % and can be achieved without any noticeable overhead in performance and area. Categories and Subject Descriptors