Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. 1: Introduction High-speed parallel multipliers are fundamental building blocks in digital signal processing systems [1]. In...

A low-power, self-timed, CMOS array multiplier, optimized for asynchronous DSP but also applicable to synchronous DSP applications is presented. In order to reduce average power consumption, a strategy termed conditional-evaluation is introduced whereby addition is carried out only in rows of the carry-save array whose bit-product is non-zero. Simulation results are presented for a transistor-level, 8-bit x 8-bit implementation which shows an average-case energy consumption of 73pJ with an average delay of 30.5ns. 1. Introduction Multiplication is an essential operation in most DSP systems and the energy efficiency of the multiplier can have a considerable impact on the overall power requirement of a DSP chip. The aim of the work presented in this paper is to develop a low-power multiplier targeted to asynchronous DSP systems. The technique is also applicable to synchronous systems if low power is of crucial importance. For low-power operation, dynamic logic (such as domino logic [1...

This paper presents a method for reducing the power dissipation of array multipliers. It is based on the insertion of transitionretaining barriers (TRB) to decrease the propagation of the useless transitions in the array that only dissipate power and do not contribute to the calculation of the final result. With three TRBs we can achieve a reduction in power dissipation of 30% in a 32\Theta32bit array multiplier with an increase in area and delay of 3.9% and 7.6% respectively. 1 Introduction Recent developments in microelectronics technology allow circuits with more and more functionality to be integrated in just one chip. Nowadays, portable applications are not only wrist clocks or calculators but computers, multi-media terminals or mobile telephones. These new applications require high computational speed and, at the same time, suffer from power dissipation constraints. Dissipation of a chip grows, among other factors, with the level of integration and the computational speed. Mult...