Results 1  10
of
140
A HighPerformance Microarchitecture with HardwareProgrammable Functional Units
 in Proceedings of the 27th Annual International Symposium on Microarchitecture
, 1994
"... This paper explores a novel way to incorporate hardwareprogrammable resources into a processor microarchitecture to improve the performance of generalpurpose applications. Through a coupling of compiletime analysis routines and hardware synthesis tools, we automatically configure a given set of t ..."
Abstract

Cited by 183 (1 self)
 Add to MetaCart
This paper explores a novel way to incorporate hardwareprogrammable resources into a processor microarchitecture to improve the performance of generalpurpose applications. Through a coupling of compiletime analysis routines and hardware synthesis tools, we automatically configure a given set of the hardwareprogrammable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of generalpurpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirelynew primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISCa RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language co...
BDS: A BDDBased Logic Optimization System
 Proc. of DAC 2000
, 2000
"... This paper describes a new BDDbased logic optimization system, BDS. It is based on a recently developed theory for BDDbased logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network e ..."
Abstract

Cited by 53 (0 self)
 Add to MetaCart
This paper describes a new BDDbased logic optimization system, BDS. It is based on a recently developed theory for BDDbased logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network environment, are described in detail. The experimental results show that BDS has a capability to handle very large circuits. It offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.
Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation
, 1992
"... Estimating maximum power dissipation for a CMOS logic network is difficult because the power dissipated by the network is typically a strong function of the network's inputs. This implies that the number of simulations which must be performed in order to find the maximum power dissipation is exponen ..."
Abstract

Cited by 50 (0 self)
 Add to MetaCart
Estimating maximum power dissipation for a CMOS logic network is difficult because the power dissipated by the network is typically a strong function of the network's inputs. This implies that the number of simulations which must be performed in order to find the maximum power dissipation is exponential in the number of inputs to the network. In this paper we show that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, we give algorithms for transforming the problem to a weighted rnaxsatisfiability problem, and then present exact and approximate algorithms for solving weighted maxsatisfiability. Algorithms for constructing the maxsatisfiability problem for both dynamic and static CMOS, where for the latter dissipation caused by glitching is considered, are presented. Also, we present efficient exact and approximate methods for solving weighted maxsatlsfiability and show that these methods are viable for largescale problems through examination of experimental results.
Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design
 INTERNATIONAL SYMPOSIUM ON LOW POWER DESIGN
, 1995
"... The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. This paper describes the development and application of algorithms that use ideas s ..."
Abstract

Cited by 46 (3 self)
 Add to MetaCart
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. This paper describes the development and application of algorithms that use ideas similar to power management, but that are applicable to logic level synthesis/design. The proposed approach is termed guarded evaluation. The main idea here is to determine, on a per clock cycle basis, which parts of a circuit are computing results that will be used, and which are not. The sections that are not needed are then “shut off”, thus saving the power used in all the useless transitions in that part of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach. While this
A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications
 In International Conference on Computer Aided Design, p. 254 – 261
, 1996
"... This paper presents a new method to express functional permissibilities for lookup table (LUT) based field programmable gate arrays (FPGAs). The method represents functional permissibilities by using sets of pairs of functions, not by incompletely specified functions. It makes good use of the prope ..."
Abstract

Cited by 45 (5 self)
 Add to MetaCart
This paper presents a new method to express functional permissibilities for lookup table (LUT) based field programmable gate arrays (FPGAs). The method represents functional permissibilities by using sets of pairs of functions, not by incompletely specified functions. It makes good use of the properties of LUTs such that their internal logics can be freely changed. The permissibilities expressed by the proposed method have the desired property that at many points of a network they can be simultaneously treated. Applications of the proposed method are also presented; a method to optimize networks and a method to remove connections that are obstacles at the routing step. Preliminary experimental results are given to show the effectiveness of our proposed method. 1 Introduction Because of their low cost, reprogrammability and rapid turnaround times, field programmable gate arrays (FPGAs) have emerged as an attractive means to implement low volume applications and prototypes[1]. FPGAs ...
Statistical Delay Calculation, a Linear Time Method
, 1997
"... This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) ..."
Abstract

Cited by 39 (1 self)
 Add to MetaCart
This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new approximate scheme to perform the delay calculations with stochastic delay values in linear time. The results are validated with Monte Carlo simulations. From a mathematical analysis some counterintuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worstcase timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits for a given delay model. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0  14%. Furthermore, due to the mathematical properties of the delay...
Hazardnonincreasing gatelevel optimization algorithms
 In ICCAD
, 1992
"... This paper presents hazardnonincreasing optimization algorithms. These are optimizations on gatelevel logic without introduction of any further static and dynamic hazards. Proofs are given for general theoretical results on hazardnonincreasing transformations which serve as the basis for these ..."
Abstract

Cited by 38 (0 self)
 Add to MetaCart
This paper presents hazardnonincreasing optimization algorithms. These are optimizations on gatelevel logic without introduction of any further static and dynamic hazards. Proofs are given for general theoretical results on hazardnonincreasing transformations which serve as the basis for these algorithms. The algorithms in this paper substantially augment the set of proven hazardnonincreasing optimization techniques in the literature. These algorithms are useful for hazardfree implementations of asynchronous designs.
Logic Synthesis of Multilevel Circuits with Concurrent Error Detection
 IEEE TRANS. CAD
, 1997
"... This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection. All errors caused by single stuckat faults are detected using a paritycheck code. The synthesis procedure (implemented in Stanford CRC's TOPS synthesis system) fully automates the design process, a ..."
Abstract

Cited by 38 (8 self)
 Add to MetaCart
This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection. All errors caused by single stuckat faults are detected using a paritycheck code. The synthesis procedure (implemented in Stanford CRC's TOPS synthesis system) fully automates the design process, and reduces the cost of concurrent error detection compared with previous methods. An algorithm for selecting a good paritycheck code for encoding the circuit outputs is described. Once the code has been selected, a new procedure called structureconstrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuckat faults cannot produce undetected errors. It is proven that the resulting implementation is path fault secure, and when augmented by a checker, forms a selfchecking circuit. The actual layout areas required for selfchecking implementations of benchmark circuits generated with the techniques described in this paper are compared with implementations using Berger codes, singlebit parity, and duplicateandcompare. Results indicate that the selfchecking multilevel circuits generated with the procedure described here are significantly more economical.
Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays
 ACM Transactions on Design Automation of Electronic Systems
, 1996
"... The increasing popularity of the field programmable gatearray (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a Ki ..."
Abstract

Cited by 31 (10 self)
 Add to MetaCart
The increasing popularity of the field programmable gatearray (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a Kinput oneoutput lookuptable (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic