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35
Efficient implementation of a BDD package
 In Proceedings of the 27th ACM/IEEE conference on Design autamation
, 1991
"... Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
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Cited by 470 (10 self)
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Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the ifthenelse (ITE) operator. A hash table is used to maintain a strong carwnical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory funcfion for the recursive ITE algorithm is implemented using a hashbased cache to decrease memory use. Memory function efficiency is improved by using rules that detect. when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and lowcost scheme for rec:ycling memory. Experimental results are given to demonstrate why various implementation tradeoffs were made. These results indicate that the package described here is significantly faster and more memoryefficient than other ROBDD implementations described in the literature. 1
Timing Driven Placement for Large Standard Cell Circuits
 Proc. DAC
, 1995
"... We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of th ..."
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Cited by 74 (1 self)
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We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of the art. Our timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. A novel pinpair algorithm controls the delay without the need for user path specification. The timing algorithm is generally applicable to hierarchical, iterative placement methods. Using this algorithm, we present results for the only MCNC standard cell benchmark circuits (fract, struct, and avq.small) for which timing information is available. We decreased the delay of the longest path of circuit fract by 36 % at an area cost of only 2.5%. For circuit struct, the delay of the longest path was decreased by 50 % at an area cost of 6%. Finally, for the large (22,000 cell) circuit avq.small, the longest path delay was decreased by 28 % at an area cost of 6 % yet only doubling the execution time. This is the first report of timing driven placement results for any MCNC benchmark circuit. 2.
FalsePathAware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation
, 2002
"... We propose a falsepathaware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths. ..."
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Cited by 54 (8 self)
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We propose a falsepathaware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit
 ITC
"... Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. ..."
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Cited by 27 (8 self)
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Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288. 1.
Computing the Area versus Delay Tradeoff Curves in Technology Mapping
, 1995
"... We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (w ..."
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Cited by 18 (5 self)
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We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture gate area  arrival time tradeoffs) at all nodes in the network, and in the second step we generate the mapping solution based on the computed delay functions and the required times at the primary outputs. For a NANDdecomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying a delay constraint if such solution exists. The algorithm has polynomial run time on a nodebalanced tree and is easily extended to mapping a directed acyclic graph (DAG). We also show how to account for the wire delays during the delay function computation step. Our results compare favorably with those of MIS2.2 mapper.
Timing Analysis of Combinational Circuits using ADD's
, 1994
"... This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADD's). The procedure we propose, implemented as an extension of the SIS synthesis system, is able to ..."
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Cited by 13 (3 self)
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This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADD's). The procedure we propose, implemented as an extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gatelevel representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worstcase primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for lowpower consumption.
Timing analysis with known false subgraphs
 IEEE/ ACM International Conference on ComputerAided Design
, 1995
"... Abstract In this paper we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another program, and supply accurate timing informa ..."
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Cited by 10 (0 self)
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Abstract In this paper we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another program, and supply accurate timing information to optimization programs such as placement and wiring. We present an efficient algorithm for the problem.
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays
 IEEE Trans. ComputerAided Design
, 1998
"... Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous, and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS ci ..."
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Cited by 7 (0 self)
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Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous, and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that the rising and falling of gate delays are either fixed or bounded. In fact the gate delay of CMOS circuits may also depend on how many and which inputs are rising or falling and the arrival times of those rising or falling inputs. For instance, the delay for a twoinput CMOS NAND gate may vary as much as a factor of two based on whether one input or two inputs are changing. We shall refer a gate delay model which considers these factors as data dependent delay model. Gray, Liu and Cavin have proposed an approach based on simulation with event pruning to deal with this type of delay mode...
Symbolic Functional and Timing Verification of TransistorLevel Circuits
 ACM/IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
, 1999
"... We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a mediumsized modern logic block. Static analysis can handle much larger circuits but is not robust with re ..."
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Cited by 7 (3 self)
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We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a mediumsized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (SirSim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a specialpurpose verification methodology.
The Role of Long and Short Paths in Circuit Performance Optimization
, 1994
"... We consider the problem of determining the smallest clock period for a combinational circuit. By considering both the long and short paths, we derive three independent bounds on the clock period. The first bound is the difference between the longest path delay and the shortest path delay, which h ..."
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Cited by 6 (0 self)
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We consider the problem of determining the smallest clock period for a combinational circuit. By considering both the long and short paths, we derive three independent bounds on the clock period. The first bound is the difference between the longest path delay and the shortest path delay, which has been studied before [6, 9, 11, 12]. The other two take the functionality of the circuit into consideration, and therefore, is usually smaller than the first one. To bring in the functionality of the circuit, we make use of a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. We also show that considering both the longest sensitizable path and the shortest destabilizing path together does not always give you a valid bound. The bounds on the clock period can be alternatively viewed as optimization objectives. At the physical level, the complexity of optimization very much depends on the number of long and short paths present and the...