Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong carwnical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory funcfion for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use. Memory function efficiency is improved by using rules that detect. when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and low-cost scheme for rec:ycling memory. Experimental results are given to demonstrate why various implementation trade-offs were made. These results indicate that the package described here is significantly faster and more memory-efficient than other ROBDD implementations described in the literature. 1

We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of the art. Our timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. A novel pin-pair algorithm controls the delay without the need for user path specification. The timing algorithm is generally applicable to hierarchical, itera-tive placement methods. Using this algorithm, we present results for the only MCNC standard cell benchmark circuits (fract, struct, and avq.small) for which timing information is available. We decreased the delay of the longest path of circuit fract by 36 % at an area cost of only 2.5%. For circuit struct, the delay of the longest path was decreased by 50 % at an area cost of 6%. Finally, for the large (21,000 cell) circuit avq.small, the longest path delay was decreased by 28 % at an area cost of 6%.

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.

Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288. 1.

We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture gate area -- arrival time tradeoffs) at all nodes in the network, and in the second step we generate the mapping solution based on the computed delay functions and the required times at the primary outputs. For a NAND-decomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying a delay constraint if such solution exists. The algorithm has polynomial run time on a node-balanced tree and is easily extended to mapping a directed acyclic graph (DAG). We also show how to account for the wire delays during the delay function computation step. Our results compare favorably with those of MIS2.2 mapper.

This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADD's). The procedure we propose, implemented as an extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gate-level representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worst-case primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for low-power consumption.

We consider the problem of determining the smallest clock period for a combinational circuit. By considering both the long and short paths, we derive three independent bounds on the clock period. The first bound is the difference between the longest path delay and the shortest path delay, which has been studied before [6, 9, 11, 12]. The other two take the functionality of the circuit into consideration, and therefore, is usually smaller than the first one. To bring in the functionality of the circuit, we make use of a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. We also show that considering both the longest sensitizable path and the shortest destabilizing path together does not always give you a valid bound. The bounds on the clock period can be alternatively viewed as optimization objectives. At the physical level, the complexity of optimization very much depends on the number of long and short paths present and the...

Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous, and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that the rising and falling of gate delays are either fixed or bounded. In fact the gate delay of CMOS circuits may also depend on how many and which inputs are rising or falling and the arrival times of those rising or falling inputs. For instance, the delay for a two-input CMOS NAND gate may vary as much as a factor of two based on whether one input or two inputs are changing. We shall refer a gate delay model which considers these factors as data dependent delay model. Gray, Liu and Cavin have proposed an approach based on simulation with event pruning to deal with this type of delay mode...

We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a medium-sized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (SirSim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a specialpurpose verification methodology.

It is known that the ISCAS85 circuit c6288 contains an exponential number of paths and more than 99 % of the path delay faults are untestable. Most ATPG tools which can efficiently handle other circuits fail on c6288. In this paper the logic structure of c6288 is studied and the main features which cause false paths are revealed. A heuristic which significantly helps the path delay fault test generation for this circuit is presented. Experimental results show that our methodology is able to efficiently generate testable paths for c6288. 1.